IDT5V9885B Integrated Device Technology, Inc., IDT5V9885B Datasheet - Page 34

• Manufacturer Part Number: IDT5V9885B
• Description: 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
• Manufacturer: Integrated Device Technology, Inc.

RAM (PROGRAMMING REGISTER) TABLES
IDT5V9885B
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
ADDR
0x4A
0x4B
0x4C
0x4D
0x4E
0x5A
0x5B
0x5C
0x5D
0x5E
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5F
7
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Default Settings)
5
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
BIT #
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
Hex Value
Register
Default
BB
BB
0C
BB
0C
BB
BB
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
03
00
00
Q2[1:0]_CONFIG1
Q3[1:0]_CONFIG1
Q4[1:0]_CONFIG1
Q5[1:0]_CONFIG1
Q6[1:0]_CONFIG1
7
OEM2[1:0]
OEM3[1:0]
OEM4[1:0]
OEM5[1:0]
OEM6[1:0]
6
PM2[1:0]_CONFIG1
PM3[1:0]_CONFIG1
PM4[1:0]_CONFIG1
PM5[1:0]_CONFIG1
PM6[1:0]_CONFIG1
5
SLEW2[1:0]
SLEW3[1:0]
SLEW4[1:0]
SLEW5[1:0]
SLEW6[1:0]
D2[7:0]_CONFIG0
D2[7:0]_CONFIG1
D2[7:0]_CONFIG2
D2[7:0]_CONFIG3
N2[7:0]_CONFIG0
N2[7:0]_CONFIG1
N2[7:0]_CONFIG2
N2[7:0]_CONFIG3
Q2[9:2]_CONFIG0
Q2[9:2]_CONFIG1
Q3[9:2]_CONFIG0
Q3[9:2]_CONFIG1
Q4[9:2]_CONFIG0
Q4[9:2]_CONFIG1
Q5[9:2]_CONFIG0
Q5[9:2]_CONFIG1
Q6[9:2]_CONFIG0
Q6[9:2]_CONFIG1
4
BIT #
INV4_1
INV5_1
Q2[1:0]_CONFIG0
Q3[1:0]_CONFIG0
Q4[1:0]_CONFIG0
Q5[1:0]_CONFIG0
Q6[1:0]_CONFIG0
3
INV4_0
INV5_0
N2[11:8]_CONFIG0
N2[11:8]_CONFIG1
N2[11:8]_CONFIG2
N2[11:8]_CONFIG3
INV2
INV3
INV6
2
34
PM2[1:0]_CONFIG0
PM3[1:0]_CONFIG0
PM4[1:0]_CONFIG0
PM5[1:0]_CONFIG0
PM6[1:0]_CONFIG0
1
LVL4[1:0]
LVL5[1:0]
0
PLL2 INPUT DIVIDER D2 SETTING
PLL2 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
PLL2 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N2[11:0]_CONFIGx - Part of PLL2 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
Total Multiplier Value M2 = N2;
Bits [7:4] in addresses 0x48, 0x49, 0x4A, and 0x4B are reserved and should be set to "0"
Configuring Output OUT2
INV2=Output Inversion for OUT2 ("0"= Non-Invert (Default), "1"=Invert);
SLEW2=Slew Rate Settings for OUT2 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM2= Output Enable Mode for OUT2output, when used with OE2 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Q2[x:x]=Output Divider "Q2" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM2[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT2, PM2 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Address 0x4C, Bits 3, 1, 0 are reserved and should be set to "0"
Configuring Output OUT3
INV3=Output Inversion for OUT3 ("0"= Non-Invert (Default), "1"=Invert);
SLEW3=Slew Rate Settings for OUT3 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM3= Output Enable Mode for OUT3 output, when used with OE3 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Q3[x:x]=Output Divider "Q3" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM3[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT3, PM3 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Address 0x50, Bits 3, 1, 0 are reserved and should be set to "0"
Configuring Output OUT4
INV4_1=Output Inversion for /OUT4 ("0"= Invert , "1"=Non-Invert (Default));
INV4_0=Output Inversion for OUT4 ("0"= Invert , "1"=Non-Invert (Default));
SLEW4=Slew Rate Settings for OUT4 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM4= Output Enable Mode for OUT4 output, when used with OE4 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
LVL4=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);
Q4[x:x]=Output Divider "Q4" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM4[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT4, PM4 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
When using LVPECL or LVDS outputs, SLEW4 must be set to "00".
Configuring Output OUT5
INV5_1=Output Inversion for /OUT5 ("0"= Invert, "1"=Non-Invert (Default));
INV5_0=Output Inversion for OUT5 ("0"= Invert, "1"=Non-Invert (Default));
SLEW5=Slew Rate Settings for OUT5 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM5= Output Enable Mode for OUT5 output, when used with OE5 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
LVL5=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);
Q5[x:x]=Output Divider "Q5" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM5[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT5, PM5 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
When using LVPECL or LVDS outputs, SLEW5 must be set to "00".
Configuring Output OUT6
INV6=Output Inversion for OUT6 ("0"= Non-Invert (Default), "1"=Invert);
SLEW6=Slew Rate Settings for OUT6 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM6= Output Enable Mode for OUT6 output, when used with OE6 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Q6[x:x]=Output Divider "Q6" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;
PM6[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));
(Note: To enable OUT6, PM6 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)
Address 0x5C, Bits 3 is reserved and should be set to "0"
Address 0x5C, Bits 1, 0 are reserved and should be set to "1"
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION