IDT5V9885B Integrated Device Technology, Inc., IDT5V9885B Datasheet - Page 8

• Manufacturer Part Number: IDT5V9885B
• Description: 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
• Manufacturer: Integrated Device Technology, Inc.

should never be disabled unless the output bank will never be used during normal operation. The output frequency range for LVTTL outputs are from 4.9KHz
to 200MHz. The output frequency range for LVPECL/LVDS outputs are from 4.9KHz to 500MHz.
SPREAD SPECTRUM GENERATION
spread are fully programmable (within limits). The programmable spread spectrum generation parameters are TSSC[3:0], NSSC[3:0], SS_OFFSET[5:0],
SD[3:0], DITH, and X2 bits. These bits are in the memory address range of 0x60 to 0x67 for PLL0 and 0x68 to 0x6F for PLL1. The spread spectrum generation
on PLL0 & PLL1 can be enabled/disabled using the TSSC[3:0] bits. To enable spread spectrum, set TSSC > '0' and set NSSC, SD[3:0], SD[5:0], and the
A[3:0] in the total M value accordingly. And to disable, set TSSC = '0'.
calculated with the TSSC bits in conjunction with the NSSC bits. Valid TSSC integer values for the modulation frequency range from 5 to 14.
of the spread spectrum waveform are mirror images of each other. The modulation frequency is also calculated based off the NSSC bits in conjunction with the
TSSC bits. Valid NSSC integer values range from 1 to 6.
the spread spectrum waveform is about the nominal M (Mnom) value. For down spread, the SS_OFFSET > '0' so the spread spectrum wavform is about the
(Mideal -1 = Mnom) value. The downspread percentage can be thought of in terms of center spread. For example, a downspread of -1% can also be considered
as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63.
SD samples for each PLL. The NSSC bits determine how many of these samples are used for the waveform. The sum of these delta-encoded samples (sigma-
delta-encoded samples) determine the amount of spread and should not exceed (63 - SS_OFFSET). The maximum spread is inversely proportional to the
nominal M integer value.
bit to '1' to enable dithering.
When X2 is '0', the amplitude remains nominal but if set to '1', the amplitude is increased by x2.
IDT5V9885B
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Note that the actual 10-bit post-divider value has a 2 added to the integer value Q and the outputs are routed through another div/2 block. The post-divider
PLL0 and PLL1 support spread spectrum generation capability, which users have the option of turning on and off. Spread spectrum profile, frequency, and
TSSC[3:0]
These bits are used to determine the number of phase/frequency detector cycles per spread spectrum cycle (ssc) steps. The modulation frequency can be
NSSC[3:0]
These bits are used to determine the number of delta-encoded samples used for a single quadrant of the spread spectrum waveform. All four quadrants
SS_OFFSET[5:0]
These bits are used to program the fractional offset with respect to the nominal M integer value. For center spread, the SS_OFFSET should be set to '0' so
SD[3:0]
These bits are used to shape the profile of the spread spectrum waveform. These are delta-encoded samples of the waveform. There are twelve sets of
DITH
This bit is for dithering the sigma-delta-encoded samples. This will randomize the least-significant bit of the input to the spread spectrum modulator. Set the
X2
This bit will double the total value of the sigma-delta-encoded-samples which will increase the amplitude of the spread spectrum waveform by a factor of two.
The following equations govern how the spread spectrum is set:
T
N
SD[3:0]
where S
Amplitude = (2*N[11:0] + A[3:0] + 1) * Spread% / 100
if 1 < Amp < 2, then set X2 bit to '1'.
SSC
SSC
= TSSC[3:0] + 2
= NSSC[3:0] * 2
K
J
= S
is the unencoded sample out of a possible 12 and SD
J+1
(unencoded) - S
(Eq. 7)
(Eq. 8)
2
J
(unencoded)
(Eq. 9)
(Eq. 10)
K
is the delta-encoded sample out of a possible 12.
8
INDUSTRIAL TEMPERATURE RANGE