MT28F160A3 Micron Technology, MT28F160A3 Datasheet - Page 12

• Manufacturer Part Number: MT28F160A3
• Description: FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
ing the ERASE SUSPEND operation, array data must be
read from a block other than the one being erased. To
resume the ERASE operation, an ERASE RESUME com-
mand (D0h) must be issued to cause the CSM to clear the
suspend state previously set. It is also possible that an
ERASE in any block can be suspended and a WRITE to
another block can be initiated. After the completion of
WRITE, the ERASE can be resumed by writing an ERASE
RESUME command (see Figure 5). It is also possible to
suspend the WRITE operation and read from another
block.
AUTOMATIC POWER-SAVING MODE
when the device is not accessed while in the active mode.
During this time, the device switches to the automatic
power saving (APS) mode. When the device switches to
this mode, I
entered automatically if no address or control lines toggle
within approximately a 300ns time-out period. At least
one transition on CE# must occur after power-up to acti-
vate this mode’s availability. The device remains in this
mode and the I/O lines retain the data from the last
access until a new read address is issued or another
operation is initiated.
RESET/ DEEP POWER-DOWN MODE
by using a special ball, RP#, to disable internal device
circuitry. When RP# is at a logic LOW level of 0.0V ±0.2V,
a much lower I
cally 1µA. This is important in portable applications where
extended battery life is a major concern.
power-down mode. A minimum of
a CSM command can be recognized. With RP# at ground,
the WSM is reset and the status register is cleared, effec-
tively eliminating accidental programming to the array
during system reset. After restoration of power, the de-
vice will be disabled until RP# is returned to V
tion, the device powers down and becomes nonfunc-
tional. Data being written or erased at that time becomes
1 Meg x 16 Enhanced Boot Block Flash Memory
MT28F160A3_3.p65 – Rev. 3, Pub. 8/01
4
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Substantial power savings are realized during periods
Very low levels of power consumption can be attained
A recovery time is required when exiting from deep
If RP# goes LOW during a PROGRAM or ERASE opera-
.com
CC
CC
is reduced to 1µA typically. This mode is
current consumption is achieved, typi-
t
RS is required before
IH
ENHANCED BOOT BLOCK FLASH MEMORY
.
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12
invalid or indeterminate, requiring that the operation be
performed again after power restoration. When RP# is set
at logic LOW, all internal circuits will be reset. Setting RP#
LOW during a PROGRAM or ERASE operation is not rec-
ommended.
STANDBY MODE
level on CE# and RP# to enter the standby mode. In the
standby mode, the outputs are placed in the high-imped-
ance state. Applying a logic HIGH level (V
and RP# reduces the current to 1µA typically. If the device
is deselected during an ERASE operation or during pro-
gramming, the device continues to draw active current
until the operation is complete.
BOOT BLOCK DATA PROTECTION
work. The only way to unlock boot blocks is to force the
WP# signal HIGH. When WP# is LOW, the boot blocks are
locked once again (see Table 5).
POWER-UP
V
be held LOW during power-up for additional protection
while V
level. After a power-up or RESET, the status register is
reset, and the device will enter the array read mode.
POWER-UP PROTECTION
tions is minimized since two consecutive cycles are re-
quired to execute either operation. When V
device does not accept any WRITE cycles, and noise
pulses < 5ns on CE# or WE# do not initiate a WRITE cycle.
POWER SUPPLY DECOUPLING
0.1µF ceramic capacitor connected between V
V
should be as close as possible to the device balls.
CC
PP
I
The WP# must be LOW for the locking mechanism to
During a power-up, it is not necessary to sequence
The likelihood of unwanted WRITE or ERASE opera-
For decoupling purposes, each device should have a
Q, V
and V
CC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
supply current is reduced by applying a logic HIGH
CC
CC
SS
and V
is ramping above V
, and between V
PP
. However, it is recommended that RP#
CC
Q and V
LKO
to a stable operative
1 MEG x 16
SS
©2001, Micron Technology, Inc.
. The capacitor
ADVANCE
CC
CC
Q) on CE#
< V
CC
and V
LKO
, the
SS
,