MT58L64L36D Micron Semiconductor, MT58L64L36D Datasheet

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MT58L64L36D

Manufacturer Part Number
MT58L64L36D
Description
(MT58LxxxLxxD) 2Mb SRAM
Manufacturer
Micron Semiconductor
Datasheet

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Part Number:
MT58L64L36D-10A
Quantity:
10
NOT RECOMENDED FOR NEW DESIGNS
2Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
• Separate +3.3V isolated output buffer supply
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
• Three chip enables for simple depth expansion and
• Clock-controlled and registered addresses, data
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 options available
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Packages
• Operating Temperature Range
GENERAL DESCRIPTION
high- speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L128L18D_C.p65 – Rev. C, Pub. 11/02
(V
WRITE
address pipelining
I/Os and control signals
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
128K x 18
100-pin TQFP
Commercial (0°C to +70°C)
The Micron
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
64K x 32
64K x 36
DD
Q)
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
MT58L128L18DT-10
®
SyncBurst
Part Number Example:
SRAM family employs
MT58L128L18D
MT58L64L32D
MT58L64L36D
MARKING
None
-7.5
-10
-6
T
DD
)
PIPELINED, DCD SYNCBURST SRAM
1
MT58L128L18D, MT58L64L32D,
MT58L64L36D
3.3V V
Deselect
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#).
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode pin (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
*JEDEC-standard MS-026 BHA (LQFP).
Asynchronous inputs include the output enable
Burst operation can be initiated with either address
Address and write control are registered on-chip to
2Mb: 128K x 18, 64K x 32/36
DD
, 3.3V I/O, Pipelined, Double-Cycle
100-Pin TQFP*
©2002, Micron Technology, Inc.

Related parts for MT58L64L36D

MT58L64L36D Summary of contents

Page 1

... MT58L128L18D (OE#), clock (CLK) and snooze enable (ZZ). There is also MT58L64L32D a burst mode pin (MODE) that selects between inter- MT58L64L36D leaved and linear burst modes. The data-out (Q), en- abled by OE#, is also asynchronous. WRITE cycles can T be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs ...

Page 2

NOT RECOMENDED FOR NEW DESIGNS 17 ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 16 ADDRESS SA0, SA1, SA REGISTER ...

Page 3

NOT RECOMENDED FOR NEW DESIGNS GENERAL DESCRIPTION (continued) DQc pins and DQPc; BWd# controls DQd pins and DQPd. GW# LOW causes all bytes to be written. Parity pins are only available on the x18 and x36 versions. The device incorporates ...

Page 4

NOT RECOMENDED FOR NEW DESIGNS ADV# ...

Page 5

NOT RECOMENDED FOR NEW DESIGNS TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32-35, 44-49, 32-35, 44-49, 80-82, 99, 81, 82, 99, 100 100 93 93 BWa BWb# – 95 BWc# – 96 BWd ...

Page 6

NOT RECOMENDED FOR NEW DESIGNS TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 84 84 ADSP ADSC MODE (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72 12, ...

Page 7

NOT RECOMENDED FOR NEW DESIGNS INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 ...

Page 8

NOT RECOMENDED FOR NEW DESIGNS TRUTH TABLE OPERATION ADDRESS CE# CE2# CE2 Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, ...

Page 9

NOT RECOMENDED FOR NEW DESIGNS ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to Vss .................................... -0.5V to +4.6V Voltage Supply DD Relative to Vss .................................... -0.5V to +4.6V V ............................................... -0. Storage ...

Page 10

NOT RECOMENDED FOR NEW DESIGNS I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (0°C ≤ T ≤ +70° +3.3V +0.3V/-0.165V unless otherwise noted DESCRIPTION CONDITIONS Device selected; All inputs ≤ V Power Supply ...

Page 11

NOT RECOMENDED FOR NEW DESIGNS TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) NOTE: 1. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 ...

Page 12

NOT RECOMENDED FOR NEW DESIGNS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C ≤ T ≤ +70° +3.3V +0.3V/-0.165V DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times ...

Page 13

NOT RECOMENDED FOR NEW DESIGNS AC TEST CONDITIONS Input pulse levels ................. V .................... V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... V Output reference levels ............................ V Output load ............................. See Figures 1 and ...

Page 14

NOT RECOMENDED FOR NEW DESIGNS SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length ...

Page 15

NOT RECOMENDED FOR NEW DESIGNS t KC CLK ADSS t ADSH ADSP# ADSC ADDRESS GW#, BWE#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# ...

Page 16

NOT RECOMENDED FOR NEW DESIGNS t KC CLK ADSS t ADSH ADSP# t ADSS ADSC ADDRESS A1 Byte write signals are ignored for first cycle when ADSP# initiates burst. BWE#, BWa#-BWd# ...

Page 17

NOT RECOMENDED FOR NEW DESIGNS t KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# (NOTE 4) t CES t CEH CE# (NOTE 2) ADV# OE ...

Page 18

NOT RECOMENDED FOR NEW DESIGNS +0.10 22.10 -0.20 20.10 ±0.10 0.65 TYP +0.06 0.32 -0.10 PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical here noted. 2. Package width and length do not include mold protrusion; allowable ...

Page 19

NOT RECOMENDED FOR NEW DESIGNS REVISION HISTORY Added “NOT RECOMENDED FOR NEW DESIGNS,” REV. C, Pub. 11/02, FINAL ........................ November/22/02 Removed 165-pin FBGA package, Rev. 6/01 .................................................................................................. June/7/01 Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00 Changed FBGA ...

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