MT58L64L36D Micron Semiconductor, MT58L64L36D Datasheet - Page 8

• Manufacturer Part Number: MT58L64L36D
• Description: (MT58LxxxLxxD) 2Mb SRAM
• Manufacturer: Micron Semiconductor

NOT RECOMENDED FOR NEW DESIGNS
TRUTH TABLE
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L128L18D_C.p65 – Rev. C, Pub. 11/02
OPERATION
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
HIGH throughout the input data hold time.
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
ADDRESS CE# CE2# CE2
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
USED
Next
Next
Next
Next
Next
Next
H
X
X
H
H
X
H
X
X
H
H
X
H
X
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
PIPELINED, DCD SYNCBURST SRAM
8
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP# ADSC# ADV# WRITE# OE#
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
2Mb: 128K x 18, 64K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
©2002, Micron Technology, Inc.
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D