MT58V512V36D Micron Technology, MT58V512V36D Datasheet

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MT58V512V36D

Manufacturer Part Number
MT58V512V36D
Description
(MT58xxxx) 16Mb SYNCBURST SRAM
Manufacturer
Micron Technology
Datasheet
16Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V ±0.165Vor 2.5V ±0.125V power supply
• Separate +3.3V or 2.5V isolated output buffer
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
• Three chip enables for simple depth expansion and
• Clock-controlled and registered addresses, data I/Os
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• 165-pin FBGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Packages
• Operating Temperature Range
*See page 34 for FBGA package marking guide.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
(V
supply (V
WRITE
address pipelining
and control signals
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
3.3V V
2.5V V
100-pin TQFP (3-chip enable)
165-pin FBGA
Commercial (0ºC to +70ºC)
1 Meg x 18
1 Meg x 18
DD
512K x 32
512K x 36
512K x 32
512K x 36
)
DD
DD
, 3.3V or 2.5V I/O
, 2.5V I/O
DD
Q)
MT58L1MY18DT-7.5
Part Number Example:
TQFP MARKING*
MT58V512V32D
MT58V512V36D
MT58L512Y32D
MT58L512Y36D
MT58V1MV18D
MT58L1MY18D
None
-7.5
-10
-6
T
F
PIPELINED, DCD SYNCBURST SRAM
1
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V V
I/O, Pipelined, Double-Cycle Deselect
GENERAL DESCRIPTION
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process.
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all addresses,
all data inputs, active LOW chip enable (CE#), two
additional chip enables for easy depth expansion (CE2,
CE2#), burst control inputs (ADSC#, ADSP#, ADV#),
byte write enables (BWx#) and global write (GW#). Note
that CE2# is not available on the T Version.
(OE#), clock (CLK) and snooze enable (ZZ). There is also
16Mb: 1 MEG x 18, 512K x 32/36
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
The Micron
Micron’s 16Mb SyncBurst SRAMs integrate a 1 Meg x
Asynchronous inputs include the output enable
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
, 3.3V or 2.5V I/O; 2.5V V
(Preliminary Package Data)
®
SyncBurst
100-Pin TQFP
165-Pin FBGA
SRAM family employs high-
1
©2000, Micron Technology, Inc.
DD
ADVANCE
, 2.5V

Related parts for MT58V512V36D

MT58V512V36D Summary of contents

Page 1

... Part Number Example: MT58L1MY18DT-7.5 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM ™ MT58L1MY18D, MT58V1MV18D, MT58L512Y32D, MT58V512V32D, MT58L512Y36D, MT58V512V36D 3.3V V I/O, Pipelined, Double-Cycle Deselect -6 -7.5 -10 NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). MT58L1MY18D GENERAL DESCRIPTION ...

Page 2

... BYTE “c” WRITE DRIVER BYTE “b” WRITE DRIVER BYTE “a” WRITE DRIVER PIPELINED ENABLE 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. OUTPUT 1 Meg OUTPUT SENSE BUFFERS MEMORY AMPS REGISTERS ARRAY 18 2 ...

Page 3

... DQa DQa DQa SA 73 DQa SA 74 DQPa Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE or a 2.5V I/O for the +2.5V DD refer to the Micron Web x32/x36 PIN # x18 1 NC/DQPa 76 V DQa DQa 78 NC ...

Page 4

... Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM PIN ASSIGNMENT (TOP VIEW) 100-PIN TQFP x18 x32/x36 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE ...

Page 5

... To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. (continued on next page) 5 DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE ©2000, Micron Technology, Inc. ...

Page 6

... No Function: These pins are internally connected to the die and have the capacitance of an input pin allowable to leave these pins unconnected or driven by signals. 6 DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE ©2000, Micron Technology, Inc. ...

Page 7

... NC/DQPd MODE (LBO#) 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. x32/x36 CE# BWc# BWb# CE2# BWE# ADSC# ADV# SA CE2 BWd# BWa# CLK GW# OE# (G#) ADSP# ...

Page 8

... Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. (continued on next page) 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE DESCRIPTION ©2000, Micron Technology, Inc. ...

Page 9

... DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd. V Supply Power Supply: See DC Electrical Characteristics and Operating DD Conditions for range. (continued on next page) 9 DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE ©2000, Micron Technology, Inc. ...

Page 10

... Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. NC – No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE DESCRIPTION ©2000, Micron Technology, Inc. ...

Page 11

... BWa# BWb Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE FOURTH ADDRESS (INTERNAL) X...X11 X...X10 X...X01 X...X00 FOURTH ADDRESS (INTERNAL) X...X11 X...X00 X...X01 X...X10 BWb ...

Page 12

... Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE CLK DQ L-H High-Z L-H High-Z L-H High-Z L-H High-Z L-H High-Z X High-Z L-H Q L-H High-Z L-H D L-H Q L-H High-Z L-H Q L-H High-Z L-H Q L-H High-Z ...

Page 13

... KC/2 for I 20mA 2.375V for t 200ms DD testing is shown in Figure 2. AC load current is higher than the stated DC values and V Q can be connected together Micron Technology, Inc., reserves the right to change products or specifications without notice. MIN MAX UNITS -0.3 0 ...

Page 14

... DD t KC/2 for I 20mA t KC/2 for I 20mA 2.375V for t 200ms DD testing is shown in Figure 4 for 2.5V I/O. AC load current is higher than the shown DC 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. MIN MAX UNITS 0.3 ...

Page 15

... C 2.5 3 2.5 3.5 CK SYMBOL TYP 46 JA 2.8 JC SYMBOL TYP Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE NOTES UNITS NOTES UNITS NOTES ºC/W 1 ºC/W 1 UNITS NOTES ºC/W 1 º ...

Page 16

... Q = +2.5V. DD and increases with faster cycle times and DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE UNITS NOTES ©2000, Micron Technology, Inc. ...

Page 17

... OEQ 3.5 t OELZ 0 t OEHZ 3 1.5 t ADSS 1.5 t AAS 1 1 1.5 t CES 1 0.5 t ADSH 0.5 t AAH 0 0 0.5 t CEH 0.5 and LOW below +2.5V, then Micron Technology, Inc., reserves the right to change products or specifications without notice. -7.5 -10 MIN MAX MIN MAX 7.5 10 133 100 2.5 3.0 2.5 3.0 4.0 5.0 1.5 1 4.2 5.0 4.2 5 4.2 4.5 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0 +3.3V ±0.165V) and Figure ...

Page 18

... /2.64) - 1.25V DD /2. /2) + 1.25V /2) - 1.25V Q Micron Technology, Inc., reserves the right to change products or specifications without notice 1.5V T Figure 1 +3.3V 317 Q 5pF 351 Figure 2 2.5V I/O Output Load Equivalents 1.25V T Figure 3 +3.3V 317 Q 5pF ...

Page 19

... CONDITIONS SYMBOL RZZ t ZZI t RZZI SNOOZE MODE WAVEFORM High-Z 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE is guaranteed after the setup time MIN MAX UNITS KC KC) ...

Page 20

... ADSH t 5.0 ns AAH t 5 CEH 4 Micron Technology, Inc., reserves the right to change products or specifications without notice Burst continued with new base address Q(A2) Q( Burst wraps around to its initial state. BURST READ DON’T CARE -6 -7.5 MIN MAX MIN ...

Page 21

... AAH 2.0 ns CEH 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADSC# extends burst. t ADSS t ADSH AAS t AAH ADV# suspends burst D(A3) D( Extended BURST WRITE DON’T CARE -6 -7.5 MIN MAX ...

Page 22

... MIN MAX UNITS SYM ADSS t 100 MHz 3.0 ns CES t 5 1.0 ns ADSH 4 2.0 ns CEH 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 D(A5) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ DON’T CARE -6 -7.5 MIN MAX MIN MAX MIN 1.5 1.5 2.0 1.5 1.5 2.0 1.5 1.5 2.0 1.5 1.5 2.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ...

Page 23

... EXIT2-DR 1 UPDATE- Figure 5 TAP Controller State Diagram SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE ©2000, Micron Technology, Inc. ...

Page 24

... Boundary Scan Register* TAP CONTROLLER * for the x18 configuration for the x36 configuration. Figure 6 TAP Controller Block Diagram 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE SS Selection TDO Circuitry ©2000, Micron Technology, Inc. ) when the ...

Page 25

... Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE plus CH). © ...

Page 26

... Do not use these instructions. TAP TIMING THTL t THTH TLTH t MVTH t THMX t DVTH t THDX DON’T CARE +2.6V Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE TLOV t TLOX UNDEFINED SYMBOL MIN MAX t THTH 100 ...

Page 27

... KHKH/2 2.4V and V Q 1.4V for must not exceed V . Control input signals (such as LD#, R/W#, etc.) may not have Micron Technology, Inc., reserves the right to change products or specifications without notice. 1.25V TDO Figure 7 TAP AC Output Load Equivalent MIN MAX UNITS 1 ...

Page 28

... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE ©2000, Micron Technology, Inc. ...

Page 29

... TBD 42 TBD 43 TBD 44 TBD 45 TBD 46 TBD 47 TBD 48 TBD 49 TBD 50 TBD 51 TBD 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE SIGNAL NAME PIN ID CLK TBD SA TBD BWa# TBD BWb# TBD SA TBD CE# TBD SA TBD SA TBD DQb TBD DQb TBD ...

Page 30

... TBD 61 TBD 62 TBD 63 TBD 64 TBD 65 TBD 66 TBD 67 TBD 68 TBD 69 TBD 70 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE SIGNAL NAME PIN ID SA TBD BWa# TBD BWb# TBD BWc# TBD BWd# TBD SA TBD CE# TBD SA TBD SA TBD NC/DQPc ...

Page 31

... FBGA PART MARKING GUIDE Micron Technology, Inc. Micron Technology, Inc., and Motorola Inc. 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE Speed Grade - -10 ...

Page 32

... MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) +0.10 22.10 -0.15 20.10 ±0.10 0.62 1.50 ±0.10 0.25 GAGE PLANE 1.00 (TYP) 0.60 ±0.15 MIN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE +0.03 0.15 -0.02 +0.06 0.32 -0.10 0.65 DETAIL A 0.10 +0.10 0.10 -0.05 1.40 ±0.05 DETAIL A ©2000, Micron Technology, Inc. ...

Page 33

... Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 SyncBurst is a trademark and Micron is a registered trademark of Micron Technology, Inc. 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 ...

Page 34

... MT58L1MY18D, Rev. 11/99, ADVANCE ........................................................................................................ Nov/11/99 Added BGA JTAG functionality 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. ADVANCE ©2000, Micron Technology, Inc. ...

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