MT9046 Zarlink Semiconductor, MT9046 Datasheet

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MT9046

Manufacturer Part Number
MT9046
Description
T1/E1 System Synchronizer with Holdover
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Supports AT&T TR62411 and Bellcore GR-1244-
CORE, Stratum 4 Enhanced and Stratum 4 timing
for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 styles of 8 KHz framing pulses
Holdover frequency accuracy of 0.2 PPM
Holdover indication
Attenuates wander from 1.9 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
Accepts reference inputs from two independent
sources
JTAG Boundary Scan
TRST
RSEL
TMS
TDO
TCK
SEC
TDI
PRI
OSCi
Master Clock
Reference
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
1149.1a
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Select
MUX
IEEE
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
Control State Machine
MS1 MS2
OSCo
Reference
Copyright 2003 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
Select
Corrector
Enable
Reference
Selected
TIE
RST
Corrector
Figure 1 - Functional Block Diagram
Circuit
HOLDOVER
TCLR
TIE
Select
State
Zarlink Semiconductor Inc.
Reference
PCCi
Virtual
1
FLOCK
Applications
Description
The MT9046 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1
primary rate transmission links. The device has
reference switching and frequency holdover capabilities
to
synchronization interruptions.
LOCK
Synchronization and timing control for Customer
Premises Equipment (CPE)
ST-BUS clock and frame pulse sources
Impairment
help
Monitor
Input
DPLL
Feedback
VDD
Select
State
maintain
MT9046AN 48 pin SSOP
T1/E1 System Synchronizer
VSS
Ordering Information
-40°C to +85°C
FS1
Frequency
Interface
Output
Select
Circuit
connectivity
MUX
FS2
with Holdover
during
Data Sheet
MT9046
temporary
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
April 2004

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