MT9046 Zarlink Semiconductor, MT9046 Datasheet - Page 4

• Manufacturer Part Number: MT9046
• Description: T1/E1 System Synchronizer with Holdover
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
33,34
Pin #
18
19
20
21
22
24
25
26
27
29
30
32
36
37
38
39
40
41
42
43
44
FLOCK
HOLD
OVER
Name
LOCK
RSEL
C16o
C19o
PCCi
MS2
MS1
TDO
C2o
C4o
C8o
C6o
FS2
FS1
NC
NC
IC
IC
IC
IC
Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to
the input reference.
Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s.
Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
Clock 19.44 MHz (CMOS Output). This output is used in OC3/STS3 applications.
Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference
(less than 500 ms locking time).
Internal Connection. Tie low for normal operation.
Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s.
Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
Holdover (CMOS Output). This output goes to a logic high whenever the PLL goes into
holdover mode.
Phase Continuity Control Input (Input). The signal at this pin affects the state changes
between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and
Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.
See Table 4.
No connection. Leave open circuit
Internal Connection. Tie low for normal operation.
Mode/Control Select 2 (Input). This input determines the state (Normal, Holdover or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.
Mode/Control Select 1 (Input).
F8o. See pin description for MS2. This pin is internally pulled down to VSS.
Reference Source Select (Input). A logic low selects the PRI (primary) reference source as
the input reference signal and a logic high selects the SEC (secondary) input. The logic level
at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled
down to VSS.
Internal Connection. Tie low for normal operation.
Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four
possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI
and SEC inputs. See Table 1.
Frequency Select 1 (Input). See pin description for FS2.
Internal Connection. Tie low for normal operation.
No Connection. Leave open Circuit
Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Zarlink Semiconductor Inc.
MT9046
The logic level at this input is gated in by the rising edge of
4
Description
Data Sheet