MT9046 Zarlink Semiconductor, MT9046 Datasheet - Page 11

• Manufacturer Part Number: MT9046
• Description: T1/E1 System Synchronizer with Holdover
• Manufacturer: Zarlink Semiconductor

MT9046
Data Sheet
Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved.
In Freerun Mode, the MT9046 provides timing and synchronization signals which are based on the master clock
frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).
±
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
32 ppm output clock
±
is required, the master clock must also be
32 ppm. See Applications - Crystal and Clock Oscillator sections.
MT9046 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
Intrinsic Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring
the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the
applicable standards. In the MT9046, the intrinsic Jitter is limited to less than 0.02 UI on the 2.048 MHz and
1.544 MHz clocks.
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards.
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
For the MT9046, two internal elements determine the jitter attenuation. This includes the internal 1.9 Hz low pass
loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5 ns/125 us.
Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the
maximum output phase slope will be limited (i.e., attenuated) to 5 ns/125 us.
The MT9046 has twelve outputs with three possible input frequencies (except for 19.44 MHz, which is internally
divided to 8 KHz) for a total of 36 possible jitter transfer functions. Since all outputs are derived from the same
signal, the jitter transfer values for the four cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to
2.048 MHz can be applied to all outputs.
It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns.
Consequently, a transfer value using different input and output frequencies must be calculated in common units
(e.g., seconds) as shown in the following example.
What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is
18 dB?
Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on
the three jitter transfer functions provided.
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Zarlink Semiconductor Inc.