MT9046 Zarlink Semiconductor, MT9046 Datasheet - Page 12

• Manufacturer Part Number: MT9046
• Description: T1/E1 System Synchronizer with Holdover
• Manufacturer: Zarlink Semiconductor

Note that the resulting jitter transfer functions for all combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz) and
outputs (8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz) for a given input signal
(jitter frequency and jitter amplitude) are the same.
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for
large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (e.g., 75% of the specified maximum jitter tolerance).
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode. For the MT9046, the Freerun accuracy is equal to the
Master Clock (OSCi) accuracy.
Holdover Accuracy
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the MT9046, the storage value is determined while
the device is in Normal Mode and locked to an external reference signal.
The absolute Master Clock (OSCi) accuracy of the MT9046 does not affect Holdover accuracy, but the change in
OSCi accuracy while in Holdover Mode does.
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull
into synchronization. The MT9046 capture range is equal to
(OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm.
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the MT9046.
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is
nominally equal to the value of the final output signal or final input signal.
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
OutputT1
OutputT1
OutputE1
OutputE1
=
=
=
=
Zarlink Semiconductor Inc.
InputT1
20
OutputT1
OutputT1
×10
MT9046


–
-------- -
20
×10
18
12
×


×


(
--------------------- -
(
=
–
------ -
1UIT1
1UIE1
(
-------------------
(
20
644ns
488ns
A
2.5UI T1
±


230 ppm minus the accuracy of the master clock
)
)
)
)
=
(
3.3UI T1
)
(
)
Data Sheet