74HCT4020D,652 NXP Semiconductors, 74HCT4020D,652 Datasheet - Page 2

• Manufacturer Part Number: 74HCT4020D,652
• Description: IC 14STAGE BINARY RIPPLE 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT4020D,652

• Package / Case: 16-SOIC (3.9mm Width)
• Logic Type: Binary Counter
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 14
• Reset: Asynchronous
• Count Rate: 47MHz
• Trigger Type: Negative Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counter Type: Binary Counters
• Logic Family: 74HCT
• Number Of Bits: 12
• Operating Supply Voltage: 4.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Timing: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4589-5; 74HCT4020D; 74HCT4020D; 933715250652

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT4020 are high-speed Si-gate CMOS
devices and are pin compatible with the “4020” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
September 1993
t
f
C
C
PHL/
max
SYMBOL
Output capability: standard
I
14-stage binary ripple counter
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
CC
PD
= input frequency in MHz
L
t
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per package
2
CP to Q
Q
MR to Q
= 25 C; t
n
V
f
to Q
o
CC
) = sum of outputs
2
n 1
0
n
f
r
i
= t
I
I
f
PARAMETER
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
2
.
The 74HC/HCT4020 are 14-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and twelve fully buffered parallel
outputs (Q
The counter is advanced on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
D
C
notes 1 and 2
in W):
L
= 15 pF; V
CONDITIONS
0
, Q
3
to Q
CC
= 5 V
13
).
11
6
17
101
3.5
19
74HC/HCT4020
HC
TYPICAL
Product specification
15
6
19
52
3.5
20
HCT
ns
ns
ns
MHz
pF
pF
UNIT