74LV4060PW,112 NXP Semiconductors, 74LV4060PW,112 Datasheet - Page 2

• Manufacturer Part Number: 74LV4060PW,112
• Description: IC 14ST BINARY RIPPLE 16-TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVr

Specifications of 74LV4060PW,112

• Package / Case: 16-TSSOP
• Logic Type: Binary Counter
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 14
• Reset: Asynchronous
• Count Rate: 90MHz
• Trigger Type: Negative Edge
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: 74LV
• Operating Supply Voltage: 1 V to 3.6 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Timing: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Timing: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2975-5; 935174990112

1. C
2. The condition is V
3. For formula on dynamic power dissipation, see the
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
t
t
f
f
C
C
C
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
1998 Jun 23
PHL
PHL
max
Wide operating voltage: 1.0 to 5.5 V
Optimized for Low Voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
Typical V
T
Typical V
= 25°C.
All active components on chip
RC or crystal oscillator configuration
Output capability: standard (except for R
I
14-stage binary ripple counter with oscillator
1
PD
CC
dissipation (P
P
f
f
S (C
following pages.
amb
i
o
PD
D
= input frequency in MHz; C
/t
= output frequency in MHz; V
category: MSI
PLH
= C
= 25°C.
SYMBOL
L
is used to determine the dynamic power
x V
PD
OLP
OHV
PACKAGES
CC
amb
x V
2
(output ground bounce) < 0.8 V at V
(output V
D
CC
x f
= 25°C; t
in mW)
2
o
) = sum of the outputs.
x f
1
= GND to V
i
+ S (C
OH
Propagation delay
RS to Q
Q
MR to Q
Maximum clock frequency
Maximum clock frequency
Input capacitance
Power dissipation capacitance per package
Power dissipation capacitance per package
r
n
= t
undershoot) > 2 V at V
to Q
f
L
x V
L
2.5 ns
n+1
3
n
= output load capacity in pF;
CC
CC
CC
CC
= supply voltage in V;
2
TEMPERATURE RANGE
x f
PARAMETER
= 2.7 V and V
TC
o
) where:
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
–40 C to +125 C
and C
CC
CC
TC
)
= 3.3 V, T
= 3.3 V,
CC
= 3.6 V
amb
OUTSIDE NORTH AMERICA
2
C
V
Notes 1, 2 and 3
CC
L
APPLICATIONS
DESCRIPTION
The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT4060.
The 74LV4060 is a 14-stage ripple-carry counter/divider and
oscillator with three oscillator terminals (RS, R
buffered outputs (Q
asynchronous master reset (MR). The oscillator configuration allows
design of either RC or crystal oscillator circuits. The oscillator may
be replaced by an external clock signal at input RS. In this case,
keep the oscillator pins (R
The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q
Q
= 15 pF
74LV4060 PW
74LV4060 DB
= 3.3 V
74LV4060 N
74LV4060 D
13
Control Counters
Timers
Frequency Dividers
Time-delay circuits
CONDITIONS
= LOW), independent of the other input conditions.
3
to Q
9
TC
NORTH AMERICA
and Q
74LV4060PW DH
74LV4060 DB
and C
74LV4060 N
74LV4060 D
11
TYPICAL
TC
to Q
) floating.
3.5
29
16
99
99
40
40
6
13
3
to Q
) and an overriding
Product specification
TC
9
74LV4060
and Q
and C
PKG. DWG. #
853-2076 19619
SOT109-1
SOT338-1
SOT403-1
SOT38-4
11
TC
to
UNIT
), ten
MHz
MHz
ns
pF
pF
pF