N74F269D,623 NXP Semiconductors, N74F269D,623 Datasheet
N74F269D,623
Specifications of N74F269D,623
N74F269D-T
N74F269D-T
Related parts for N74F269D,623
N74F269D,623 Summary of contents
Page 1
Rev. 05 — 25 March 2010 1. General description The 74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry look-ahead for easy cascading and a U/D input to ...
Page 2
... NXP Semiconductors 4. Functional diagram U CEP 13 CET Fig 1. Logic symbol 74F269_5 Product data sheet 001aai979 Fig 2. All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 8-bit bidirectional binary counter CTR DIV256 24 M1 [LOAD] M2 [COUNT [UP] M4 [DOWN 256 / 6− 1,7D ...
Page 3
... NXP Semiconductors Dn Fig 3. Logic diagram 74F269_5 Product data sheet 23 DETAIL DETAIL DETAIL DETAIL DETAIL DETAIL DETAIL DETAIL U/D 12 CEP 13 CET TOGGLE DETAIL All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 74F269 8-bit bidirectional binary counter 001aal296 © NXP B.V. 2010. All rights reserved. ...
Page 4
CEP CET least significant 8-bit counter Fig 4. Synchronous multistage counting scheme ...
Page 5
... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SO24 and SSOP24 package 5.2 Pin description Table 2. Pin description Symbol Pin U GND CEP 12 CET 23, 22, 21, 20, 18, 17, 16 One FAST Unit Load (UL) is defined as 20 μA in HIGH state, 0.6 μA in LOW state. ...
Page 6
... NXP Semiconductors 6. Functional description 6.1 Function table [1] Table 3. Function table Operating modes Input CP ↑ Parallel load (Dn to Qn) ↑ ↑ Count up (increment) ↑ Count down (decrement) ↑ Hold (do nothing) ↑ [ HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition ...
Page 7
... NXP Semiconductors U/D CEP and CET SEQUENCE Fig 6. Typical timing sequence 74F269_5 Product data sheet 253 254 255 LOAD COUNT UP INHIBIT All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 74F269 8-bit bidirectional binary counter 255 254 253 ...
Page 8
... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output current O T ambient temperature amb T storage temperature stg [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. ...
Page 9
... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage IK V HIGH-level output OH voltage V LOW-level output OL voltage I input leakage current I I HIGH-level input current LOW-level input current IL I output current O I supply current CC [1] All typical values are measured at V [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second ...
Page 10
... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure Symbol Parameter Conditions t set-up time HIGH Dn to CP; see su( CP; see CEP or CET to CP; see U/D to CP; see t set-up time LOW Dn to CP; see su( CP; see CEP or CET to CP; see U/D to CP; see ...
Page 11
... NXP Semiconductors Measurement points are given 1 and V are the typical output voltage levels that occur with the output load Fig 8. Input (CET) to output (TC) propagation delay Measurement points are given 1 and V are the typical output voltage levels that occur with the output load. ...
Page 12
... NXP Semiconductors The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given 1 and V are the typical output voltage levels that occur with the output load Fig 11. Count enable inputs (CEP and CET) and clock input (CP) set-up and hold times The shaded areas indicate when the input is permitted to change for predictable output performance ...
Page 13
... NXP Semiconductors negative V M pulse positive V M pulse Input pulse definition Test data is given in Table Definitions for test circuit Load capacitance including jig and probe capacitance Load resistance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 13 ...
Page 14
... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 15
... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 15. Package outline SOT340-1 (SSOP24) ...
Page 16
... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12 “ ...
Page 17
... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 18
... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74F269_5 Product data sheet http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 74F269 8-bit bidirectional binary counter © NXP B.V. 2010. All rights reserved. ...
Page 19
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline ...