CS98000-CQ Cirrus Logic, Inc., CS98000-CQ Datasheet - Page 12

• Manufacturer Part Number: CS98000-CQ
• Description: Internet DVD (iDVD) Chip Solution
• Manufacturer: Cirrus Logic, Inc.

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3.2.12 Sub-picture Processor
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3.2.13 System Functions
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3.3
The CS98000 includes two powerful, proprietary
32-bit RISC processors, called RISC, with optimiz-
ing C compiler support and source level debugger.
The RISC has an instruction set that is a superset of
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Supports 4:2:0, 4:2:2, YUV655, RGB565 and
RGB555 frame buffer inputs.
High quality scaling using a vertical and a hor-
izontal 16 taps polyphase programmable filter,
to support any size image up to 768x576.
Programmable sharpening and de-blocking fil-
ters.
5 taps programmable adaptative anti-flicker fil-
tering for Graphics source.
Master or Slave video sync configuration.
Outputs 4:2:2 video in CCIR-601 or CCIR-656
format.
Multiple video plains overlay (main video/vid-
eo input/picture_in_picture picture/on_screen
display/cursor).
Gamma Correction.
Run-length decode DVD sub-pictures and
SVCD OGT formats
Hardware vertical scaling supports NTSC-PAL
format conversion
16 level alpha blending
Provides hardware cursor mode for non-DVD
applications
128 and 208-pin PQFP packages.
All I/O pins are 3 V with 5 V tolerance.
Advanced 0.25 micron CMOS technology.
Internal processors run at 81 MHz
Supports Low power modes and clock shutoff.
RISC Processor
MIPS R3000. In addition to the standard MIPS
R3000 instruction code, the RISC processor also
has a MAC engine, which performs multiply/accu-
mulate in 2 cycles in a pipelined fashion with C
support,
throughout. There are other instructions that are de-
signed to help with performing MPEG1/2 decod-
ing. The CS98000 fully supports many Real Time
Operating Systems (RTOS) such as WindRiver
OS and ATI. The RISC processor co-ordinates on-
chip multi-threaded tasks, as well as system activi-
ties such as remote control and front panel control.
3.4
The CS98000 contains a proprietary digital signal
processor (DSP) called DSP, which is optimized
for audio and sound applications. The DSP per-
forms 32 bit simple integer operations, and has a 24
bit fixed point logic unit, with a 54 bit accumulator.
There are 32 general-purpose registers, and eight
independent address generation registers, featur-
ing: post-increment ALU, linear and circular buffer
operations, bit reverse ALU operations, and dual
operand read from memory. The multiply-accumu-
lator has single-cycle throughput, with two cycle
latency. The DSP is optimized for bit packing and
unpacking operations. The interface to main mem-
ory is designed for handling flexible block sizes
and skip counts.
3.5
The DRAM Interface performs the SDRAM con-
trol and arbitration functions for all the other mod-
ules in the CS98000. The DRAM interface services
and arbitrates a number of clients and stores their
code and/or data within the local memory. This ar-
bitration and scheduling guarantees the allocation
of sufficient bandwidth to the various clients. The
DRAM Interface supports up to 32 MB. For a typ-
ical DVD player application, CS98000 requires
4 MB memory space.
DSP Processor
Memory Control
effectively
achieving
single
CS98000
DS525PP1
cycle
®