ACS-1024-LG Photon Vision Systems, Inc., ACS-1024-LG Datasheet - Page 13

• Manufacturer Part Number: ACS-1024-LG
• Description: Image Sensor, CMOS|CCD, 1026x1026 Pixels, 132pin LCC
• Manufacturer: Photon Vision Systems, Inc.

When the device is in MASTER mode, the on-chip state machine uses the information in the setup registers to control the
imager. These registers are 12 bits wide.
parallel bus, pins 1-7 and 112-116. These are accessed via a 5 bit address bus ADD, pins 80, 82, 84, 86, and 88. See figures 3
and 4 for access timing.
REGION OF INTEREST REGISTERS:
The device has the ability to control 2 regions of interest simultaneously. This allows for faster sub frame readout. The ROI
Registers must contain a valid non-zero value for that ROI to operate. Note that at least one of the ROI’s must be setup in
order to scan video. The ROI’s can overlap, but note that the pixels read in the first ROI are valid in the overlap region. When
the second ROI is read, the same pixels when read for the other region will not be valid.
SETUP REGISTERS:
REGISTER
ADDRESS
100
101
102
103
105
105
90
91
92
93
94
95
96
97
98
99
(Hex)
0
1
2
3
4
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
Product DATASHEET ACS PDS0003 Subject to change without notice. Page 13 of 26
C8
C7
A7
A6
B7
B6
C6
A5
B5
A4
A3
B4
C5
B3
A2
C4
NAME
ROI 0 Row Start
ROI 0 Row Stop
ROI 0 Col. Start
ROI 0 Col. Stop
ROI 1 Row Start
DIG_DATA_ENA
DATA_0_LSB
DATA_1
DATA_2
DATA_3
DATA_4
DATA_5
DATA_6
DATA_7
DATA_8
DATA_9
REG_DATA_0
REG_DATA_1
REG_DATA_2
REG_DATA_3
REG_DATA_4
DESCRIPTION
Row Address of pixel for ROI 0 to Start – must be less than REG. 1.
Row Address of pixel for ROI 0 to Stop – Must be greater than REG. 0.
Column Address of pixel for ROI 0 to Start – must be less than REG. 3.
Column Address of pixel for ROI 0 to Stop – Must be greater than
REG. 2.
Row Address of pixel for ROI 1 to Start – must be less than REG. 5.
The register data can be accessed via the bi-directional REG_DATA 12 bit wide
Photon Vision Systems, Inc.
Digital Input
Digital video Data
enable.
Tri-state Output
Digitized video Bit 0
LSB
Tri-state Output
Digitized video Bit 1
Tri-state Output
Digitized video Bit 2
Tri-state Output
Digitized video Bit 3
Tri-state Output
Digitized video Bit 4
Tri-state Output
Digitized video Bit 5
Tri-state Output
Digitized video Bit 6
Tri-state Output
Digitized video Bit 7
Tri-state Output
Digitized video Bit 8
Tri-state Output
Digitized Video Bit 9
Bi-directional I/O
Bi-directional I/O
Bi-directional I/O
Bi-directional I/O
Bi-directional I/O
Copyright© 2002 Rev A
When true low digital video, 1X clock, ACTIVE and FRAME are
output.
When false theses outputs are tri-stated
Digital video is output as Bit 0, LSB.
Digital video is output as Bit 1.
Digital video is output as Bit 2.
Digital video is output as Bit 3.
Digital video is output as Bit 4.
Digital video is output as Bit 5.
Digital video is output as Bit 6
Digital video is output as Bit 7.
Digital video is output as Bit 8.
Digital video is output as Bit 9.
Setup Register data bit 0, LSB.
See Register setup table for more information
Pin must be connected whenever in SLAVE mode, do not float.
Setup Register data bit 1.
See Register setup table for more information
Pin must be connected whenever in SLAVE mode, do not float.
Setup Register data bit 2.
See Register setup table for more information
Pin must be connected whenever in SLAVE mode, do not float.
Setup Register data bit 3.
See Register setup table for more information
Pin must be connected whenever in SLAVE mode, do not float.
Setup Register data bit 4, MSB.
See Register setup table for more information
Pin must be connected whenever in SLAVE mode, do not float.
DEFAULT
VALUE
0
1024
0
1024
0