ACS-1024-LG Photon Vision Systems, Inc., ACS-1024-LG Datasheet - Page 16

• Manufacturer Part Number: ACS-1024-LG
• Description: Image Sensor, CMOS|CCD, 1026x1026 Pixels, 132pin LCC
• Manufacturer: Photon Vision Systems, Inc.

Figure 3.
Figure 4.
TIMING DIAGRAMS: SETUP REGISTER WRITE AND READ
The following timing diagrams illustrate setup register writing and reading. It is important to note that the writing and reading
of the setup registers is asynchronous, that is these operations are not clock dependant.
CAUTION: Do not change the state of N_WR whenever N_CS is low. Register reading and writing can only occur when the
device is in MASTER mode. Note minimum pulse duration is 1 master clock pulse.
Note that a register write cycle will occur on the rising edge of N_CS while N_WR is low. A register read cycle occurs on the
falling edge of N_CS whenever N_WR is high. Data is written to, or read from, the registers, within 50ps of the edge transition.
This simplifies timing of signals to access the registers.
N_CS transition, therefore the timing diagrams below do not show actual times. For simplicity of operation, you can use the
CLK1X as an event, if desired. For example, write the Address and data to the ADD and DATA buses, then while holding
those values, on subsequent clocks, strobe the N_CS and N_WR lines.
READ CYCLE: Figure 4. Apply valid address, 0-15 (hex) to address bus lines ADD0-ADD4. Data will be output to the
REG_DATA Bus, REG_DATA_0 - REG_DATA_11 on the high to low transition of N_CS, and will remain valid until N_CS
is taken high again. Note diagram shows setting N_WR signal high only while N_CS is high.
WRITE CYCLE: Figure 4. Apply valid address, 0-15(hex) to address bus lines ADD0-ADD4, and valid data (12 bits) to the
REG_DATA bus, REG_DATA_0 - REG_DATA_11.
high.
Minimum tsu – 5ns, Minimum tcs – 5ns, minimum th – 10ns. The maximum time for these signals is that the summation of all
three must be less than one frame time.
FRAME TIMING DIAGRAM
Figure 5 shows video output for a 3 by 3 ROI, again with a 40MHz CLK2X.
Product DATASHEET ACS PDS0003 Subject to change without notice. Page 16 of 26
tsu
tcs
th
Photon Vision Systems, Inc.
Copyright© 2002 Rev A
Note diagram shows setting N_WR signal low only while N_CS is
You only must have valid address and data on the buses during a