IDT7028 Integrated Device Technology, IDT7028 Datasheet - Page 11

• Manufacturer Part Number: IDT7028
• Description: 64k X16 Dual-port Ram
• Manufacturer: Integrated Device Technology

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
DATA
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = V
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
DATA
ADDR
ADDR
WH
WB
BUSY
L
R/W
OUT "B"
is only for the 'Slave' version.
must be met for both BUSY input (SLAVE) and output (MASTER).
= CE
IN "A"
IL
"A"
"A"
"B"
"B"
for the reading port.
R
IL
= V
(SLAVE), BUSY is an input. Then for this example BUSY
IL,
refer to Chip Enable Truth Table.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
APS
is ignored for M/S = V
"B"
t
WB
goes HIGH.
(3)
t
BAA
"A"
= V
MATCH
IL
t
IH
WC
6.42
(SLAVE).
11
t
and BUSY
WP
(2)
t
WP
"B"
input is shown above.
MATCH
Industrial and Commercial Temperature Ranges
IL
t
DW
t
WDD
)
VALID
t
WH
(1)
4836 drw 12
t
DDD
(3)
t
BDA
.
t
DH
IH
4836 drw 11
t
)
BDD
(2,4,5)
VALID