IDT7028 Integrated Device Technology, IDT7028 Datasheet - Page 6

• Manufacturer Part Number: IDT7028
• Description: 64k X16 Dual-port Ram
• Manufacturer: Integrated Device Technology

AC Test Conditions
Waveform of Read Cycles
DATA
BUSY
Timing of Power-Up Power-Down
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. t
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
6. Refer to Chip Enable Truth Table.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
UB, LB
ADDR
has no relation to valid output data.
BDD
R/W
OUT
OUT
CE
OE
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
(6)
IH
.
CE
I
I
CC
SB
(6)
t
t
t
t
t
AA
ACE
AOE
LZ
ABE
(1)
(4)
Figures 1 and 2
(4)
(4)
(5)
(4)
GND to 3.0V
3ns Max.
t
PU
1.5V
1.5V
AOE
4836 tbl 11
t
RC
50%
, t
ACE
, t
t
BDD
AA
6
DATA
or t
(3,4)
Figure 1. AC Output Test Load
BUSY
BDD
OUT
INT
.
347Ω
VALID DATA
Industrial and Commercial Temperature Ranges
t
PD
5V
4836 drw 06
4836 drw 03
(4)
893Ω
30pF
50%
DATA
t
HZ
.
(2)
t
OUT
OH
Figure 2. Output Test Load
* Including scope and jig.
(for t
347Ω
LZ
, t
HZ
, t
WZ
, t
5V
4836 drw 05
OW
4836 drw 04
893Ω
)
5pF*