IDT7028 Integrated Device Technology, IDT7028 Datasheet - Page 12

• Manufacturer Part Number: IDT7028
• Description: 64k X16 Dual-port Ram
• Manufacturer: Integrated Device Technology

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = V
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = V
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
INTERRUPT TIMING
t
t
t
t
AS
WR
INS
INR
ADDR
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
BUSY
ADDR
ADDR
BUSY
Symbol
and
APS
CE
CE
is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
"A"
"B"
"A"
"B"
"B"
"A"
"B"
"B"
Interrupt Set Time
Interrupt Reset Time
Address Set-up Time
Write Recovery Time
t
IH
APS
)
(1)
(2)
t
APS
(2)
t
BAA
MATCHING ADDRESS "N"
Parameter
ADDRESS "N"
t
BAC
ADDRESSES MATCH
12
Industrial and Commercial Temperature Ranges
t
BDC
t
BDA
Min.
____
____
Com'l Only
0
0
7028L15
Max.
____
____
15
15
Min.
Com'l & Ind
____
____
0
0
7028L20
IH
Max.
4836 drw 13
____
____
4836 drw 14
)
20
20
(1,3)
4836 tbl 15
Unit
ns
ns
ns
ns