IDT7028 Integrated Device Technology, IDT7028 Datasheet - Page 14

• Manufacturer Part Number: IDT7028
• Description: 64k X16 Dual-port Ram
• Manufacturer: Integrated Device Technology

Truth Table VI — Example of Semaphore Procurement Sequence
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7028.
2. There are eight semaphore flags written to via I/O
3. CE = V
Functional Description
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7028 has an automatic power down feature controlled
by CE. The CE
permits the respective port to go into a standby mode when not selected
(CE = V
is permitted.
Interrupts
or message center) is assigned to each port. The left port interrupt flag
Truth Table V —
Address BUSYArbitration
NOTES:
1. Pins BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
4. Refer to Chip Enable Truth Table.
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
CE
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
X
H
X
L
The IDT7028 provides two ports with separate control, address and
If the user chooses the interrupt function, a memory location (mail box
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
and enable inputs of this port. If t
when BUSY
L
IH
CE
). When a port is enabled, access to the entire memory array
X
X
IH
H
L
R
, SEM = V
Inputs
L
R
and BUSY
0
Functions
outputs are driving LOW regardless of actual logic level on the pin.
and CE
NO MATCH
A
A
MATCH
MATCH
MATCH
OR
OL
IL
-A
-A
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
15L
15R
R
1
control the on-chip power down circuitry that
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7028 are
APS
BUSY
(2)
H
H
H
is not met, either BUSY
L
(1)
Outputs
BUSY
D
0
(2)
- D
H
H
H
0
and read from all I/O's (I/O
R
L
1
1
1
1
1
1
1
(4)
15
0
0
0
0
(1)
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
Left
L
Function
or BUSY
Inhibit
Normal
Normal
Normal
Write
4836 tbl 17
D
(3)
0
R
- D
= LOW will result. BUSY
15
1
1
1
1
1
1
1
1
0
0
0
Right
14
0
(INT
(HEX), where a write is defined as CE
IV. The left port clears the interrupt through access of address location
FFFE when CE
port interrupt flag (INT
location FFFF (HEX) and to clear the interrupt flag (INT
must read the memory location FFFF. The message (16 bits) at FFFE or
FFFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations FFFE and FFFF are not
used as mail boxes, but as part of the random access memory. Refer to
Table IV for the interrupt operation.
-I/O
15
L
). These eight semaphores are addressed by A
) is asserted when the right port writes to memory location FFFE
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
L
L
Industrial and Commercial Temperature Ranges
and BUSY
= OE
R
L
) is asserted when the left port writes to memory
= V
R
outputs can not be LOW simultaneously.
IL
, R/W is a "don't care". Likewise, the right
Status
R
= R/W
0
R
-A
= V
2
.
IL
(1,2,3)
per Truth Table
R
), the right port
4836 tbl 18