TDA9105 ST Microelectronics, TDA9105 Datasheet - Page 15

• Manufacturer Part Number: TDA9105
• Description: DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
• Manufacturer: ST Microelectronics

OPERATING DESCRIPTION (continued)
Figure 8 : Principle Diagram
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A ”CRC” filter is generally used (see
Figure 9).
PLL1 is inhibited by applying a high level on Pin 14
(PLLinhib) which is a TTL compatible input. The inhibi-
tion results from the opening of a switch located be-
tween the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by charge and dis-
charge of the capacitor, by a current proportionnal
to the current in the resistor. typical thresholds of
sawtooth are 1.6V and 6.4V (see Figure 10).
The control voltage of the VCO is typically com-
prised between 1.6V and 6V (see Figure 10). The
theoreticalfrequencyrange of this VCO is in the ratio
1
external components and the circuit itself, the effec-
Figure 10 : Details of VCO
3.75, but due to spread and thermal drift of
H-SYNC
(1.6V < V
17
Loop
Filter
12
12
INTERFACE
< 6V)
INPUT
H-LOCKCAP
11
R0
13
LOCKDET
COMP1
E2
I
0
4 I
H-LOCKOUT
I
2
2
2
0
0
High
Low
tive frequency range has to be smaller (e.g. 30kHz
the control voltage is equal to 1.6V typ. and the VCO
oscillates on its lowest frequency (free frequency).
The synchro frequencyhas to be always higher than
the free frequency and a margin has to be taken. As
an example for a synchro range from 30kHz to
85kHz, the suggested free frequency is 27kHz.
Figure 9
C0
85kHz). In the absence of synchronisation signal
CHARGE
10
PUMP
6.4V
1.6V
6.4V
1.6V
0
0.75T T
PLL1INHIB
INHIBITION
ADJUST
PHASE
H-POS
14
PLL
15
PLL1F
12
FLIP FLOP
PLL1F R0
RS
3.2V
12
11
VCO
C0
OSC
10
TDA9105
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