TDA9105 ST Microelectronics, TDA9105 Datasheet - Page 22

• Manufacturer Part Number: TDA9105
• Description: DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
• Manufacturer: ST Microelectronics

TDA9105
OPERATING DESCRIPTION (continued)
VERTICAL PART (continued)
Function
When the synchronisation pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, C
the typical free running frequency is 100Hz.
Typical free running frequency can be calculated
by :
A negative or positive TTL level pulse applied on
Pin 34 (VSYNC) can synchronise the ramp in the
frequency range [fmin, fmax]. This frequency range
depends on the external capacitor connected on
Pin 27. A capacitor in the range [150nF, 220nF] is
recommanded for application in the following
range : 50Hz to 120Hz.
Typical maximum and minimum frequency, at 25 C
and without any correction (S correction or C cor-
rection), can be calculated by :
f
If S or C corrections are applied, these values are
slighty affected.
If an external synchronisation pulse is applied, the
internal oscillator is automaticaly caught but the
amplitude is no more constant. An internal correc-
tion is activated to adjust it in less than half a
second: the highest voltage of the ramp on Pin 27
is sampled on the sampling capacitor connected on
Pin 25 (VAGCCAP) at each clock pulse and a
transconductance amplifier generates the charge
current of the capacitor. The ramp amplitude be-
comes again constant.
It is recommanded to use a AGC capacitor with low
leakage current. A value lower than 100nA is man-
datory.
Pin 36, Vfly is the vertical flyback input used to
generate the composite blanking signal. If Vfly is
not used, (V
nected to this input.
DC Control Adjustments
Then, S and C correction shapes can be added to
this ramp. This frequency independent S and C
corrections are generated internally; their ampli-
22/32
max
= 2.5 f
f
0
0
REF
and f
Hz
- 0.5), at minimum, must be con-
min
1.5 10
= 0.33 f
5
C
OSC
0
1
nF
OSC
= 150nF,
tude are DC adjustable on Pin 28 (V
Pin 29 (COR-C).
S correction is non effective for V
V
C correction is non effective for COR-C grounded
and maximum for :
COR-C = V
Endly, the amplitude of this S and C corrected ramp
can be adjusted by the voltage applied on Pin 31
(V
(V
of this stage is typically 30% when voltage applied
on Pin 31 is in the range V
DC value of this ramp is kept constant in the
frequency range , for any correction applied on it.
Its typical value is : V
A DC voltage is available on Pin 32 (V
driven by the voltage applied on Pin 33 (V
For a voltage control range between V
3/4 V
V
So, the V
of V
ture varies.
Basic Equations
In first approximation, the amplitude of the ramp on
Pin 30 (V
with V
On Pin 32 (V
lated by : V
V
The current available on Pin 27
(when V
I
C
f synchronisation frequency
The recommanded capacitor value on Pin 25
(V
internal closed loop.
OSC
REF
DCOUT
V
POS
OSC
AMP
OUT
AGC
OUT
OUT
/4 and maximum for V
= 3/8 V
V
V
) to drive an external power stage. The gain
is the voltage applied on Pin 33.
). The adjusted ramp is available on Pin 30
: capacitor connected on Pin 27
) is 470nF. Its ensures a good stability of the
- V
REF
MID
MID
CAP
. It increases the accuracy when tempera-
= 7/16 V
SAMP
MID
DCOUT
OUT
, the voltage available on Pin 32 is :
is the middle value of the ramp on Pin 27
= 7/16 V
= V
DCOUT
REF
= (V
) is :
DCOUT
REF
= V
27
/4 or COR-C = 3/4 V
CAP
voltage is correlated with DC value
, ramp with fixed amplitude.
REF
REF
=V
C
), the voltage (in volts) is calcu-
- V
REF
OSC
/4) is :
MID
DCOUT
MID
300mV.
) [1 + 0.16 (V
; typically 3.5V
+ 0.16 (V
f
REF
SAMP
= V
/4 to 3/4 V
MID
= 3/4 V
SAMP
= 7/16 V
POS
AMP
REF
DCOUT
- V
lower than
SAMP
REF
- V
REF
.
REF
POS
REF
REF
/4 and
) and
.
). It is
REF
. The
)
/2).
/2)]
.