TDF8599 NXP Semiconductors, TDF8599 Datasheet - Page 20

• Manufacturer Part Number: TDF8599
• Description: I2C-bus controlled dual channel 43 W/2 W single channel 85 W/1 W class-D power amplifier
• Manufacturer: NXP Semiconductors

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NXP Semiconductors
TDF8599_1
Product data sheet
8.6.2.2 Recommended start-up sequence with DC load detection enabled
Remark: DC load detection identifies a short circuited speaker as a valid speaker load.
OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,
performs diagnostics on shorted loads. However, the diagnostics are performed after the
DC load detection cycle has finished and once the amplifier is in Operating mode.
The result of the DC load detection is stored in DB1[D4] and DB2[D4].
Table 12.
Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must
be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load
detection is interrupted by a sudden large change in supply voltage (triggered by UVP or
OVP) or if the amplifier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC
load enable bit DB2[D2] must be reset after the DC load protection cycle to release any
amplifier hang-up. Once the DC load detection cycle has finished, DC load detection can
be restarted by toggling the DC load detection enable bit IB2[D2]. However, this can only
be used if both amplifier channels have not been enabled with bit IB1[D1] or bit IB2[D1].
See
for detailed information.
The flow diagram
detection without starting the amplifiers. After a DC load detection cycle finishes without
setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is
toggled).
To limit the maximum number of DC load detection cycle loops, a counter and limit have
been added. The loop exits after the predefined number of cycles (COUNTMAX), if the
DC load detection cycle finishes with an invalid detection.
Depending on the application needs the invalid DC load detection cycle can be handled
as follows:
A valid DC load detection cycle does not affect the normal amplifier start-up timing.
DC load bits DB1[D4] and DB2[D4]
0
0
1
•
•
the amplifier can be started without DC load detection
the DC load detection loop can be executed again
Section 8.6.2.2 “Recommended start-up sequence with DC load detection enabled”
Interpretation of DC load detection bits
(Figure
Rev. 01 — 13 November 2008
20) illustrates the TDF8599’s ability to perform a DC load
OCP bits DB1[D3] and DB2[D3]
0
1
0
Class-D power amplifier with load diagnostics
TDF8599
Meaning
speaker load
shorted load
open load
© NXP B.V. 2008. All rights reserved.
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