LM4681 National Semiconductor, LM4681 Datasheet - Page 16

• Manufacturer Part Number: LM4681
• Description: Stereo CLASS D Audio Power Amplifier
• Manufacturer: National Semiconductor

www.national.com
General Features
8. If ENABLE is logic-low for more than 8 CLK pulses then
only the first 8 data bits will be latched and activated at rising
edge of eighth CLK.
9. ENABLE must remain logic-high for at least 50ns (t
10. Coincidental rising or falling edges of CLK and ENABLE
are not allowed. If CLK is to be held logic-high after the data
HP Outputs
–64.94
–64.94
–56.94
–47.94
–42.94
–37.94
–33.94
–31.94
–28.94
–25.94
–22.94
–20.94
–18.94
–16.94
–14.94
–12.94
–10.94
–8.94
–6.94
–4.94
–2.94
–0.94
10.06
12.06
13.06
11.06
1.06
3.06
6.06
7.07
8.06
9.06
Gain (dB)
Class D
Outputs
–48.03
–48.03
–36.03
–31.03
–26.03
–21.03
–17.03
–15.03
–12.03
–9.03
–6.03
–4.03
–2.03
–0.03
13.97
15.97
17.97
19.97
22.97
23.97
24.97
25.97
26.97
27.97
28.97
29.97
11.97
1.97
3.97
5.97
7.97
9.97
(Continued)
Bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TABLE 1. Volume Control Settings
EL
).
Bit 3
16
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
transmission, the falling edge of CLK must occur at least
50ns (t
next set of data.
Volume Control
The internal Stereo Volume Control is set by changing bits 0
through 4 in the SPI interface, as shown in table 3 below.
CS
) before ENABLE transitions to logic-low for the
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1