DS1023 Dallas Semiconducotr, DS1023 Datasheet - Page 2

• Manufacturer Part Number: DS1023
• Description: 8-Bit Programmable Timing Element
• Manufacturer: Dallas Semiconducotr

DS1023
On-chip gating is provided to allow the device to provide a pulse width modulated output, triggered by
the input with duration set by the programmed value.
Alternatively the output signal may be inverted on chip, allowing the device to perform as a free-running
oscillator if the output is (externally) connected to the input.
PROGRAMMING
The device programming is identical to the DS1020/DS1021. Note, however, that the serial clock and
data pins are shared with three of the parallel input pins.
The
/S pin controls the same function as “Mode Select” on the DS1020/DS1021 (but with reversed
P
polarity). A low logic level on this pin enables the parallel programming mode. LE must be at a high
logic level to alter the programmed value; when LE is taken low the data is latched internally and the
parallel data inputs may be altered without affecting the programmed value.
This is useful for
multiplexed bus applications. For hard-wired applications LE should be tied to a high logic level.
When
/S is high serial programming is enabled. LE must be held high to enable loading or reading of
P
the internal register, during which time the delay is determined by the previously programmed value.
Data is clocked in MSB to LSB order on the rising edge of the CLK input. Data transfer ends and the
new value is activated when LE is taken low.
PARALLEL MODE (
/S = 0)
P
In the PARALLEL programming mode, the output of the DS1023 will reproduce the logic state of the
input after a delay determined by the state of the eight program input pins P0 - P7. The parallel inputs
can be programmed using DC levels or computer-generated data. For infrequent modification of the
delay value, jumpers may be used to connect the input pins to V
or ground. For applications requiring
CC
frequent timing adjustment, DIP switches may be used. The latch enable pin (LE) must be at a logic 1 in
hardwired implementations.
Maximum flexibility is obtained when the eight parallel programming bits are set using computer-
generated data. When the data setup (t
) and data hold (t
) requirements are observed, the enable pin
DSE
DHE
can be used to latch data supplied on an 8-bit bus. Latch enable must be held at a logic 1 if it is not used
to latch the data. After each change in delay value, a settling time (t
or t
) is required before input
EDV
PDV
logic levels are accurately delayed.
SERIAL MODE (
/S = 1)
P
In the SERIAL programming mode, the output of the DS1023 will reproduce the logic state of the input
after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup
(t
) and data hold (t
) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of
DSC
DHC
the serial clock (CLK). The latch enable pin (LE) must be at a logic 1 to load or read the internal 8-bit
input register, during which time the delay is determined by the last value activated. Data transfer ends
and the new delay value is activated when latch enable (LE) returns to a logic 0. After each change, a
settling time (t
) is required before the delay is accurate.
EDV
As timing values are shifted into the serial data input (D), the previous contents of the 8-bit input register
are shifted out of the serial output pin (Q) in MSB-to-LSB order. By connecting the serial output of one
DS1023 to the serial input of a second DS1023, multiple devices can be daisy-chained (cascaded) for
programming purposes (Figure 1). The total number of serial bits must be eight times the number of units
daisy-chained and each group of 8 bits must be sent in MSB-to-LSB order.
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