DS2164Q

Manufacturer Part NumberDS2164Q
DescriptionG.726 ADPCM Processor
ManufacturerDallas Semiconducotr
DS2164Q datasheet
 


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FEATURES
§ Compresses/expands 64kbps PCM voice
to/from either 32kbps, 24kbps, or 16kbps
§ Dual fully independent channel architecture;
device can be programmed to perform either:
- two expansions
- two compressions
- one expansion and one compression
§ Interconnects directly to combo-codec
devices
§ Input to output delay is less than 375ms
§ Simple serial port used to configure the
device
§ On-board time-slot assigner-circuit (TSAC)
function allows data to be input/output at
various time slots
§ Supports Channel Associated Signaling
§ Each channel can be independently idled or
placed into bypass
§ Available hardware mode requires no host
processor; ideal for voice storage
applications
§ Backward-compatible with the DS2165Q
ADPCM processor chip
§ Single +5V supply; low-power CMOS
technology
§ Available in 28-pin PLCC
DESCRIPTION
The DS2164Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been
optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three
different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from)
either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT
Recommendation G.726. The DS2164Q can switch compression algorithms on-the-fly. This allows the
user to make maximum use of the available bandwidth on a dynamic basis.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device errata,
click here: http://www.maxim-ic.com/errata.
G.726 ADPCM Processor
PIN ASSIGNMENT (Top View)
NC
5
A0
6
A1
7
A2
8
A3
9
A4
10
A5
11
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DS2164Q
4
3
2
1
28
27
26
FSY
25
YOUT
24
CS
23
DS2164Q
SDI
22
SCLK
21
XOUT
20
NC
19
12
13 14
15
16
17
18
28-Pin PLCC
070802

DS2164Q Summary of contents

  • Page 1

    ... Available in 28-pin PLCC DESCRIPTION The DS2164Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from) either 32kbps, 24kbps, or 16kbps ...

  • Page 2

    ... Connecting SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2164Q by the serial port through inputs SCLK, SDI, and write to the DS2164Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the address/command byte (ACB), followed by a byte to configure the control register (CR) for either the channel ...

  • Page 3

    ... Y Frame Sync. 8kHz frame sync for the Y-side PCM interface. Y Data Clock. Data clock for the Y-side PCM interface; must be synchronous with FSY. Y Data In. Sampled on falling edge of CLKY during selected time slots. Positive Supply. 5. for normal operation select the serial port; connect to V DS2164Q to SS ...

  • Page 4

    ... Bypass operates on bytewide (8 bits) slots when CP/ (4 bits) slots when CP/ is cleared and m-law (U/ A-law ( CR.2. If BYP and IPD are cleared, then CP/ expanded PCM coding is independently selected for the X and Y channels A determines if the input data compressed DS2164Q is set and on nibble-wide EX ...

  • Page 5

    ... Algorithm Reset 0 = normal operation 1 = reset algorithm for selected channel Bypass 0 = normal operation 1 = bypass selected channel Data Format 0 = A-law 1 = m-law Algorithm Select 2 (Table 2) Channel Coding 0 = expand (decode) selected channel 1 = compress (encode) selected channel DS2164Q (LSB (LSB) AS2 U/ A CP/ EX ...

  • Page 6

    ... LSB of input time slot register FUNCTION Reserved. Must be 0 for proper operation Reserved. Must be 0 for proper operation MSB of output time slot register — — — — LSB of output time slot register AS0 DS2164Q (LSB) D0 (LSB) D0 ...

  • Page 7

    ... Note: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX or CLKY after the frame sync. Figure 7. m-LAW PCM INTERFACE Figure 8. m-LAW ADPCM INTERFACE and U/ (Figures 7 through 10). For and it is set to expect m-law data DS2164Q . The number EX ...

  • Page 8

    ... Figure 9. A-LAW PCM INTERFACE Figure 10. A-LAW ADPCM INTERFACE DS2164Q ...

  • Page 9

    ... X and SDI 19 CS NOTES: 1) SCLK must be connected When both channels are idled, power consumption is significantly reduced. 3) The DS2164Q powers up within 800ms after either channel is returned to active from an idle state. , and CP/ A CP/ EX (Channel X) AS0/AS1/AS2 U/ A (Channel X) CP/ ...

  • Page 10

    ... Hold A1 and A4 low during a hardware reset; take both A1 and A4 high after the 64kpbs to/from 24kbps has returned high (allow 3ms after returns high before taking A1 and A4 high). 64kbps to/from 16kbps Connect both A1 and Figure 11. DS2164Q CONNECTION TO CODEC/FILTER * Suggested Codec/Filters TP305X National Semiconductor ETC505X STMicroelectronics MC1455XX Motorola, Inc ...

  • Page 11

    ... Figure 12. PCM AND ADPCM I/O EXAMPLE Note 1: The bit after the LSB in the 24kbps ADPCM output is only a 1 when the DS2164Q is operated in the software mode and is programmed to perform 24kbps compression; in all other configurations ...

  • Page 12

    ... INPUT TO OUTPUT DELAY With all three compressions algorithms, the total delay, from the time the PCM data sample is captured by the DS2164Q to the time it is output, is always less than 375ms. The exact delay is determined by the input and output time slots selected for each channel. ...

  • Page 13

    ... DD SYMBOL MIN OUT (V SYMBOL MIN I DDA I DDPD DS2164Q -1.0V to +7.0V 0°C to +70°C -55°C to +125°C See IPC/JEDEC J-STD-020A (T = 0°C to +70°C) A MAX UNITS NOTES +0 +25°C) A TYP MAX UNITS NOTES ± ...

  • Page 14

    ... T = 0°C to +70° TYP MAX UNITS 3906 150 ns 150 ±10 0°C to +70° TYP MAX UNITS 100 DS2164Q NOTES NOTES 1 ...

  • Page 15

    ... 250 CCH t 250 CWH t 50 SCC = 0.8V, and 10ns maximum rise and fall times ±10 0°C to +70° TYP MAX UNITS 100 DS2164Q NOTES ...

  • Page 16

    ... Figure 13. PCM INTERFACE AC TIMING DIAGRAM Figure 14. MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 15. SERIAL PORT AC TIMING DIAGRAM Note: SCLK can be either high or low when CS is taken low DS2164Q ...

  • Page 17

    ... PLCC INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 — B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 0.430 L1 0.060 — — e1 0.050 BSC CH1 0.042 0.048 DS2164Q ...