DS2482-100 Dallas Semiconducotr, DS2482-100 Datasheet - Page 10

• Manufacturer Part Number: DS2482-100
• Description: Single-Channel 1-Wire Master
• Manufacturer: Dallas Semiconducotr

Write Configuration
1-Wire Reset
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
D2h
Configuration Byte
Writes a new configuration byte. The new settings take effect immediately.
NOTE: When writing to the Configuration register, the new data is
accepted only if the upper nibble (bits 7 to 4) is the one's complement of
the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Defining the features for subsequent 1-Wire communication.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and parameter are not acknowledged if 1WB = 1 at the
time the command code is received and the command is ignored.
None; the Configuration register is updated on the rising SCL edge of the
configuration byte acknowledge bit.
None
Configuration register (to verify write)
RST set to 0
1WS, SPU, PPM, APU updated
B4h
None
Generates a 1-Wire Reset/Presence Detect cycle (Figure 5) at the 1-Wire
line. The state of the 1-Wire line is sampled at t
reported to the host processor through the Status register, bits PPD and
SD.
To initiate or end any 1-Wire communication sequence.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code is not acknowledged if 1WB = 1 at the time the command
code is received and the command is ignored.
t
command code acknowledge bit.
Begins maximum 262.5ns after the falling SCL edge of the command
code acknowledge bit.
Status register (for busy polling)
1WB (set to 1 for t
PPD is updated at t
SD is updated at t
1WS, PPM, APU apply
RSTL
+ t
RSTH
+ maximum 262.5ns, counted from the falling SCL edge of the
10 of 21
RSTL
RSTL
RSTL
+ t
+ t
+ t
RSTH
SI
MSP
),
,
SI
and t
MSP
and the result is