EM6605 EM Microelectronic, EM6605 Datasheet - Page 5

• Manufacturer Part Number: EM6605
• Description: 4 bit Microcontroller
• Manufacturer: EM Microelectronic

1. Operating modes
The EM6605 has two low power dissipation modes:
STANDBY and SLEEP. Figure 4 is a transition diagram
for these modes.
1.1. STANDBY Mode
Executing a HALT instruction puts the EM6605 into
STANDBY mode. The voltage regulator, oscillator,
Watchdog timer, interrupts and timer/event counter are
operating. However, the CPU stops since the clock
related to instruction execution stops. Registers, RAM,
and I/O pins retain their states prior to STANDBY mode.
STANDBY is cancelled by a RESET or an Interrupt
request if enabled.
Table 2 : shows the state of the EM6605 functions in
STANDBY and SLEEP modes.
1.2. SLEEP Mode
Writing to the SLEEP bit in the IntRq register puts the
EM6605 in SLEEP mode. The oscillator stops and most
functions of the EM6605 are inactive. To be able to write
the SLEEP bit, the SLmask bit must first be set to 1. In
SLEEP mode only the voltage regulator and RESET
input are active. The RAM data integrity is maintained.
SLEEP mode may be cancelled only by a RESET at the
terminal pin of the EM6605. The RESET must be high
for at least 2µsec.
Due to the cold start characteristics of the oscillator, waking up from SLEEP mode may take some time to
guarantee that the oscillator has started correctly. During this time the circuit is in RESET and the strobe
output STB/RST is high. Waking up from SLEEP mode clears the SLEEP flag but not the SLmask bit. By
reading SLmask one can therefore determine if the EM6605 was powered up (SLmask = 0), or woken
from SLEEP mode (SLmask = 1).
2. Power Supply
The EM6605 is supplied by a single external power supply between Vdd and Vss, the circuit reference
being at Vss (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the
oscillator and internal logic. Output drivers are supplied directly from the external supply Vdd. A typical
connection configuration is shown in Figure 3.
For Vdd less then 2.0V it is recommended that Vdd is connected directly to Vreg
For Vdd>2.2V then the configuration shown in Fig.3 should be used.
Figure 4.Mode Transition diagram
Table 2.StandBy and Sleep Activities
FUNCTION
Oscillator
Instruction Execution Stopped
Registers and Flags
Interrupt Functions
RAM
Timer/Counter
Watchdog
I/O pins
Supply VLD
Reset pin
© EM Microelectonic-Marin SA, 02/99, Rev. B/243
Retained
Active
STANDBY SLEEP
Active
Retained
Active
Active
Active
Stopped
Active
EM6605
Stopped
Reset
Stopped
Stopped
Stopped
Retained
Stopped
Stopped
High-Z or
Retained
Active
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