EM6605 EM Microelectronic, EM6605 Datasheet - Page 6

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EM6605

Manufacturer Part Number
EM6605
Description
4 bit Microcontroller
Manufacturer
EM Microelectronic
Datasheet
3. Reset
To initialise the EM6605, a system RESET must be executed. There are four methods of doing this:
(1)
(2)
(3)
(4)
During any of these RESET’s the STB/RST output pin is high.
Figure 5.System reset generation
3.1. Oscillation detection circuit
At power on, the built-in voltage regulator starts to follow the supply voltage until Vdd becomes higher than
Vreg. Since it is Vreg which supplies the oscillator and this needs time to stabilise, Power-On-Reset with
the oscillation detection circuit therefore counts the first 64 or 128 oscillator clocks after power-on and
holds the system in RESET. The system will consequently remain in RESET during Cold Start time - t
(see table 6) for at least 2msec or 4msec second after power up from the 32kHz clock (*f1) - see Table 6
for frequencies.
After power up the Analogue Watchdog circuit monitors the oscillator. If it stops for any reason other then
SLEEP mode, then a RESET is generated and the STB/RES pin is driven high.
3.2. Reset Pin
During active or STANDBY mode the RESET terminal has a debouncer to reject noise and therefore must
be active high for at least 2ms = t
in CIRQD register. (see / Table 32)
At power on, or when cancelling SLEEP mode, the debouncer is not active and so RESET must satisfy the
filter time constant (typ. 1µsec) such that the RESET must be active high for at least 2µsec.
© EM Microelectronic-Marin SA, 02/99, Rev. B/243
6
Initial RESET from the oscillation detection circuit.
External RESET from the RESET PIN.
External RESET by simultaneous high input to terminals PA0..PA3.
(Combinations defined by metal option)
Watchdog RESET (software option).
debS
/ 16ms = t
debL
(*f1) (CLK = 32kHz) - software selectable by DebCK
EM6605
CoSt

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