XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 131

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Pinout Descriptions
CP132: 132-ball Chip-scale Package
The XC3S250E and the XC3S500E FPGAs are available in
the 132-lead chip-scale package, CP132. Both devices
share a common footprint for this package as shown in
Table 10
Table 10
by bank number and then by pin name. Pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
Physically, the D14 and K2 balls on the XC3S250E FPGA
are not connected but should be connected to VCCINT to
maintain density migration compatibility.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 10: CP132 Package Pinout
10
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
and
lists all the CP132 package pins. They are sorted
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0/HSWAP
IO_L11P_0
Figure
XC3S250E
XC3S500E
Pin Name
3.
CP132
Ball
C12
A13
A12
B12
B11
C11
A10
C6
C9
A9
B9
B7
A7
B6
C5
B5
C4
B4
B3
A3
GCLK
GCLK
GCLK
VREF
GCLK
GCLK
GCLK
VREF
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 10: CP132 Package Pinout
Bank
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
VCCO_0
VCCO_0
IO/A0
IO/VREF_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IO_L05N_1/A7/RHCLK3/
TRDY1
IO_L05P_1/A8/RHCLK2
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4/
IRDY1
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L08N_1/A1
IO_L08P_1/A2
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP/VREF_1
VCCO_1
VCCO_1
IO/D5
XC3S250E
XC3S500E
Pin Name
Advance Product Specification
DS312-4 (v1.1) March 21, 2005
CP132
M12
M14
Ball
N14
N13
M13
H12
H13
G13
G14
D12
D13
C13
C14
G12
B10
F12
K13
K14
F13
F14
E13
L14
L13
J12
J14
J13
C8
B8
A6
P4
RHCLK/
RHCLK/
RHCLK/
RHCLK/
RHCLK/
RHCLK/
RHCLK/
RHCLK/
VCCO
VCCO
VCCO
VCCO
GCLK
GCLK
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
DUAL
Type
R