XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 85

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Functional Description
In-System Programming Support
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is High, the I/Os have pull-up resistors to
the V
programming hardware then has direct access to the paral-
lel Flash pins. The programming access points are high-
lighted in the gray boxes in
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM pro-
gramming algorithms and receives programming data from
the host via the FPGA’s JTAG interface. See Chapter 11 in
"Embedded System Tools Reference
78
I
Recommend
open-drain
In a production application, the parallel Flash PROM is
PROG_B
CCO
driver
TMS
TDO
TCK
TDI
JTAG
2.5V
input on their respective I/O bank. The external
Not available
in VQ100
package
BPI Mode
‘0’
‘1’
A
‘0’
‘0’
P
HSWAP
M2
M1
M0
CSI_B
RDWR_B
TDI
TMS
TCK
PROG_B
Figure 55
Spartan-3E
FPGA
VCCINT
+1.2V
GND
VCCAUX
VCCO_0
VCCO_1
VCCO_2
Figure 56: Daisy-Chaining from BPI Flash Mode
A[23:17]
CSO_B
A[16:0]
INIT_B
DONE
BUSY
D[7:0]
CCLK
LDC0
LDC1
LDC2
and
Manual".
HDC
TDO
Figure
VCCO_0
+2.5V
V
V
56.
www.xilinx.com
I
+2.5V
CE#
OE#
WE#
BYTE#
DQ[15:7]
DQ[7:0]
A[n:0]
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
By default, MultiBoot mode is disabled. To trigger a Multi-
Boot event, assert a Low pulse lasting at least 300 ns on the
MultiBoot Trigger (MBT) input to the STARTUP_SPARTAN3E
library primitive.
power up, the FPGA loads itself from the attached parallel
Flash PROM. In this example, the M0 mode pin is Low so
the FPGA starts at address 0 and increments through the
Flash PROM memory locations. After the FPGA completes
configuration, the application loaded into the FPGA per-
forms a board-level or system test using FPGA logic. If the
test is successful, the FPGA triggers a MultiBoot event,
causing the FPGA to reconfigure from the opposite end of
the Flash PROM memory. This second configuration con-
tains the FPGA application for normal operation.
VCC
GND
V
x8/x16
PROM
Flash
x8 or
D
V
Parallel
Slave
Mode
‘1’
‘1’
‘0’
‘0’
P
Figure 57
HSWAP
M2
M1
M0
CCLK
CSI_B
RDWR_B
TDI
TMS
TCK
PROG_B
Spartan-3E
FPGA
VCCINT
+1.2V
GND
shows an example usage. At
Advance Product Specification
VCCAUX
VCCO_0
VCCO_1
VCCO_2
DS312-2 (v1.1) March 21, 2005
CSO_B
INIT_B
DONE
D[7:0]
BUSY
LDC0
LDC1
LDC2
HDC
TDO
VCCO_0
VCCO_1
+2.5V
V
DS312-2_50_021405
CCLK
D[7:0]
CSO_B
PROG_B
TCK
TMS
DONE
INIT_B
R