XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 39

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Functional Description
Table 21: Block RAM Attributes (Continued)
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports.
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
Table 22: Block RAM Function Table
32
Data Output Latch Synchronous
Set/Reset Value
Data Output Latch Behavior during Write
(see
GSR
1
0
0
0
0
0
Block RAM Data
EN
X
0
1
1
1
1
Loaded During Configuration
SSR
Function
X
X
1
1
0
0
Table 22
Input Signals
WE
Operations)
X
X
0
1
0
1
CLK
X
X
↑
↑
↑
↑
describes the data opera-
Global Set/Reset Immediately After Configuration
ADDR
Synchronous Set/Reset During Write RAM
Write RAM, Simultaneous Read Operation
addr
addr
addr
X
X
X
Immediately After Configuration
Read RAM, no Write Operation
pdata
pdata
DIP
SRVAL_A, SRVAL_B
Synchronous Set/Reset
SRVAL (single-port)
X
X
X
X
WRITE_MODE
(dual-port)
RAM Disabled
Attribute
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Data
Data
DI
X
X
X
X
RAM(pdata)
The waveforms for the write operation are shown in the top
half of
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
RAM(data)
No Chg
No Chg
SRVAL
SRVAL
pdata
DOP
INIT
X
Output Signals
Figure
Hex value the width of the chosen port.
WRITE_FIRST, READ_FIRST, NO_CHANGE
WRITE_MODE = WRITE_FIRST
WRITE_MODE = NO_CHANGE
WRITE_MODE = READ_FIRST
30,
RAM(data)
RAM(data)
No Chg
No Chg
SRVAL
SRVAL
Figure
INIT
data
DO
X
31, and
Possible Values
Advance Product Specification
RAM(addr)
RAM(addr)
RAM(addr)
RAM(addr)
DS312-2 (v1.1) March 21, 2005
INITP_xx
← pdata
← pdata
← pdata
← pdata
No Chg
No Chg
No Chg
No Chg
Parity
Figure
RAM Data
32. When the WE
RAM(addr)
RAM(addr)
RAM(addr)
RAM(addr)
← pdata
← pdata
INIT_xx
← data
← data
No Chg
No Chg
No Chg
No Chg
Data
R