LM3S6422 Luminary Micro, Inc, LM3S6422 Datasheet - Page 357

• Manufacturer Part Number: LM3S6422
• Description: Lm3s6422 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

14.2.3.2 MAC Layer FIFOs
July 25, 2008
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For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes.
For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames,
up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO,
an overflow error is indicated.
For details regarding the TX and RX FIFO layout, refer to Table 14-1 on page 357. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in
the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been
written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field overlaps
words in the FIFO. However, for the RX FIFO, the beginning of the next frame is always on a word
boundary.
Table 14-1. TX & RX FIFO Organization
FIFO Word Read/Write
Sequence
1st
2nd
The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values
can appear in this field. A minimum frame size is required to properly meet the IEEE standard.
If necessary, the data field is extended by appending extra bits (a pad). The pad field can have
a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets.
The MAC module automatically inserts pads if required, though it can be disabled by a register
write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame
Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received
is too large to fit into the Ethernet Controller’s RAM.
Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this
field is computed over destination address, source address, length/type, data, and pad fields
using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time.
For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by
the CRC bit in the MACTCTL register. For received frames, this field is automatically checked.
If the FCS does not pass, the frame is not placed in the RX FIFO, unless the FCS check is
disabled by the BADCRC bit in the MACRCTL register.
Word Bit Fields
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
Preliminary
TX FIFO (Write)
Data Length LSB
Data Length MSB
DA oct 1
DA oct 2
DA oct 3
DA oct 4
DA oct 5
DA oct 6
LM3S6422 Microcontroller
RX FIFO (Read)
Frame Length LSB
Frame Length MSB
357