LM3S6422 Luminary Micro, Inc, LM3S6422 Datasheet - Page 66
LM3S6422
Manufacturer Part Number
LM3S6422
Description
Lm3s6422 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S6422.pdf
(473 pages)
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System Control
6.3
Table 6-1. System Control Register Map
66
Offset
0x01C
0x05C
0x000
0x004
0x008
0x010
0x014
0x018
0x030
0x034
0x040
0x044
0x048
0x050
0x054
0x058
0x060
0x064
0x070
0x100
0x104
Name
DID0
DID1
DC0
DC1
DC2
DC3
DC4
PBORCTL
LDOPCTL
SRCR0
SRCR1
SRCR2
RIS
IMC
MISC
RESC
RCC
PLLCFG
RCC2
RCGC0
RCGC1
3.
4.
5.
Register Map
Table 6-1 on page 66 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note:
Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
0x0001.71BF
0x8F03.0FC0
0x0000.7FFD
0x0780.3AD1
0x007F.002F
0x5000.007F
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0780.2810
0x0307.0011
0x00000000
0x00000000
0x00000000
0x00000040
0x00000000
Reset
-
-
-
-
Preliminary
Description
Device Identification 0
Device Identification 1
Device Capabilities 0
Device Capabilities 1
Device Capabilities 2
Device Capabilities 3
Device Capabilities 4
Brown-Out Reset Control
LDO Power Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL Translation
Run-Mode Clock Configuration 2
Run Mode Clock Gating Control Register 0
Run Mode Clock Gating Control Register 1
July 25, 2008
page
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