LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 253

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
Offset 0x414
Type RO, reset 0x0000.0000
June 02, 2008
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
RO
RO
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 252). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
RIS
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value
0
1
RO
RO
23
0
7
0
Description
Corresponding pin interrupt requirements not met.
Corresponding pin interrupt has met requirements.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RIS
RO
RO
19
0
3
0
LM3S5632 Microcontroller
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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