LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 587

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
USBTXCSRHn Device Mode
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1)
Base 0x4005.0000
Offset 0x113
Type R/W, reset 0x00
June 02, 2008
Bit/Field
Bit/Field
AUTOSET
R/W
3
2
1
0
7
6
7
0
R/W
ISO
6
0
MODE
R/W
AUTOSET
DMAMOD
5
0
DTWE
Name
Name
FDT
ISO
DT
DMAEN
R/W
4
0
FDT
R/W
3
0
Type
W1S
Type
R/W
R/W
R/W
R/W
R/W
DMAMOD
R/W
2
0
RO
Reset
Reset
1
0
reserved
0
0
0
0
0
0
Preliminary
RO
0
0
Description
Force Data Toggle
The CPU sets this bit to force the endpoint data toggle to switch and
the data packet to be cleared from the FIFO, regardless of whether an
ACK was received. This can be used by interrupt transmit endpoints
that are used to communicate rate feedback for isochronous endpoints.
DMA Request Mode
The CPU sets this bit to select DMA Request Mode 1 and clears it to
select DMA Request Mode 0.
Note:
Data Toggle Write Enable
The CPU writes a 1 to this bit to enable the current state of the transmit
endpoint data toggle to be written (see DT). This bit is automatically
cleared once the new value is written.
Data Toggle
When read, this bit indicates the current state of the transmit endpoint
data toggle. If DTWE is High, this bit may be written with the required
setting of the data toggle. If DTWE is Low, any value written to this bit is
ignored.
Description
Auto Set
If the CPU sets this bit, TXRDY is automatically set when data of the
maximum packet size (value in USBTXMAXPn) is loaded into the
transmit FIFO. If a packet of less than the maximum packet size is
loaded, then TXRDY must be set manually.
Note:
ISO
The CPU sets this bit to enable the transmit endpoint for isochronous
transfers, and clears it to enable the transmit endpoint for bulk or interrupt
transfers.
This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
This bit should not be set for either high-bandwidth
isochronous or high-bandwidth interrupt endpoints.
LM3S5632 Microcontroller
587