LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 591

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
USBRXCSRLn Device Mode
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1)
Base 0x4005.0000
Offset 0x116
Type R/W, reset 0x00
June 02, 2008
Bit/Field
Bit/Field
CLRDT
W1S
3
2
1
0
7
6
5
7
0
STALLED
R/W0C
6
0
DATAERR / NAKTO
STALL
R/W
STALLED
ERROR
5
0
RXRDY
CLRDT
STALL
Name
Name
FULL
FLUSH
W1S
4
0
DATAERR
RO
3
0
R/W0C
R/W0C
R/W0C
R/W0C
Type
Type
W1S
R/W
RO
R/W0C
OVER
2
0
FULL
RO
Reset
Reset
1
0
0
0
0
0
0
0
0
RXRDY
Preliminary
R/W0C
0
0
Description
Data Error / NAK Timeout
When operating in ISO mode, this bit is set when RXRDY is set if the
data packet has a CRC or bit-stuff error and cleared when RXRDY is
cleared. In Bulk mode, this bit is set when the receive endpoint is halted
following the receipt of NAK responses for longer than the time set as
the NAK Limit by the USBRXINTERVALn register. The CPU should
clear this bit to allow the endpoint to continue.
Error
The USB sets this bit when three attempts have been made to receive
a packet and no data packet has been received. The CPU should clear
this bit. An interrupt is generated when the bit is set.
Note:
FIFO Full
This bit is set when no more packets can be loaded into the receive
FIFO.
Receive Packet Ready
This bit is set when a data packet has been received. The CPU should
clear this bit when the packet has been unloaded from the receive FIFO.
An interrupt is generated when the bit is set.
Description
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
Endpoint Stalled
This bit is set when a STALL handshake is transmitted. The CPU should
clear this bit.
Send Stall
The CPU writes a 1 to this bit to issue a STALL handshake. The CPU
clears this bit to terminate the stall condition.
Note:
This bit is only valid when the receive endpoint is operating
in Bulk or Interrupt mode. In ISO mode, it always returns zero.
This bit has no effect where the endpoint is being used for
isochronous transfers.
LM3S5632 Microcontroller
591