LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 500

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Controller Area Network (CAN) Module
500
A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
Figure 17-2. CAN Bit Time
Table 17-3. CAN Protocol Ranges
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. The sum
of Prop_Seg and Phase_Seg1 (as TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte,
and SJW and BRP are combined in the other byte.
In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to be
programmed to a numerical value that is one less than its functional value; so instead of values in
the range of [1..n], values in the range of [0..n-1] are programmed. That way, for example, SJW
(functional range of [1..4]) is represented by only two bits. Therefore, the length of the bit time is
(programmed values):
[TSEG1 + TSEG2 + 3] × t
or (functional values):
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] × t
The data in the bit timing registers are the configuration input of the CAN protocol controller. The
Baud Rate Prescalar (configured by BRP) defines the length of the time quantum, the basic time
unit of the bit time; the Bit Timing Logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
Parameter
BRP
Sync_Seg
Prop_Seg
Phase_Seg1
Phase_Seg2
SJW
a. tSeg1 = Prop_Seg + Phase_Seg1
b. tSeg2 = Phase_Seg2
c. Phase_Seg1 = Phase_Seg2 or Phase_Seg1 + 1 = Phase_Seg2
Sync_
Seg
Range
[1 .. 32]
1 t
[1 .. 8] t
[1 .. 8] t
[1 .. 8] t
[1 .. 4] t
q
Prop_Seg
Quantum
q
q
q
q
1 Time
( t
Remark
Defines the length of the time quantum t
Fixed length, synchronization of bus input to system clock
Compensates for the physical delay times
May be lengthened temporarily by synchronization
May be shortened temporarily by synchronization
May not be longer than either Phase Buffer Segment
q
q
)
q
tSeg1
a
Preliminary
Nominal CAN Bit Time
a
Phase_Seg1
q
c
Sample
Point
q
Phase_Seg2
tSeg2
b
June 02, 2008