LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 619

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Offset 0x40C
Type R/W, reset 0x0000.0000
June 02, 2008
Host
Device
Bit/Field
31:1
RO
RO
0
31
15
0
0
RO
RO
Register 92: USB External Power Control Interrupt Status and Clear
(USBEPCISC), offset 0x40C
USBEPCISC is instantiated in a USB unit in a wrapper around the USB controller/PHY IP. This
32-bit register specifies the masked interrupt status of the two-pin external power interface. It also
provides a method to clear the interrupt state.
USB External Power Control Interrupt Status and Clear (USBEPCISC)
Base 0x4005.0000
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
PF
RO
RO
28
12
0
0
RO
RO
27
11
0
0
R/W1C
Type
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
0
reserved
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Power Fault Interrupt Status and Clear
Specifies whether a detected power fault has generated an interrupt.
Writing a 1 to this bit clears it and the USBEPCRIS PF bit. This bit is
set if the USBEPCRIS PF bit is set (by hardware) and the USBEPCIM
PF bit is set.
Value
0
1
RO
RO
23
0
7
0
Description
No Interrupt
The hardware has not generated an interrupt for a detected
power fault condition.
Interrupt
The hardware has generated an interrupt for a detected power
fault condition.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S5652 Microcontroller
RO
RO
18
0
2
0
RO
RO
17
0
1
0
R/W1C
RO
PF
16
0
0
0
619