LM3S3759 Luminary Micro, Inc, LM3S3759 Datasheet - Page 551

• Manufacturer Part Number: LM3S3759
• Description: Lm3s3759 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
USBTXCSRL1 Device Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
June 02, 2008
Bit/Field
Bit/Field
R/W0C
INCTX
3
2
1
0
7
6
7
0
CLRDT
W1S
6
0
STALLED
R/W0C
ERROR
FIFONE
5
0
FLUSH
TXRDY
CLRDT
INCTX
Name
Name
STALL
R/W
4
0
FLUSH
W1C
3
0
R/W0C
R/W0C
R/W0C
R/W0C
W1C
Type
Type
W1S
UNDRN
R/W0C
2
0
FIFONE
R/W0C
Reset
Reset
1
0
0
0
0
0
0
0
Preliminary
TXRDY
R/W1S
0
0
Description
Flush FIFO
The CPU writes a 1 to this bit to flush the latest packet from the endpoint
transmit FIFO. The FIFO pointer is reset, the TXRDY bit is cleared, and
an interrupt is generated. FLUSH may be set simultaneously with TXRDY
to abort the packet that is currently being loaded into the FIFO.
Note:
Error
The USB sets this bit when three attempts have been made to send a
packet and no handshake packet has been received. When the bit is
set, an interrupt is generated, TXRDY is cleared, and the FIFO is
completely flushed. The CPU should clear this bit.
Note:
FIFO Not Empty
The USB controller sets this bit when there is at least one packet in the
transmit FIFO.
Transmit Packet Ready
The CPU sets this bit after loading a data packet into the FIFO. It is
cleared automatically when a data packet has been transmitted. An
interrupt is generated at this point. TXRDY is also automatically cleared
prior to loading a second packet into a double-buffered FIFO.
Description
Incomplete Transmit
When the endpoint is being used for high-bandwidth isochronous
transfers, this bit is set to indicate where a large packet has been split
into 2 or 3 packets for transmission but insufficient IN tokens have been
received to send all the parts.
Note:
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
FLUSH should only be used when TXRDY is set. At other times,
it may cause data to be corrupted. Also note that, if the FIFO
is double-buffered, FLUSH may need to be set twice to
completely clear the FIFO.
This is valid only when the endpoint is operating in Bulk or
Interrupt mode.
Only valid for isochronous transfers.
LM3S3759 Microcontroller
551