LM3S3759 Luminary Micro, Inc, LM3S3759 Datasheet - Page 68

• Manufacturer Part Number: LM3S3759
• Description: Lm3s3759 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
6.1.5.3
6.1.5.4
6.1.5.5
6.1.5.6
68
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 85). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) on page 81 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
USB PLL Frequency Configuration
The USB PLL is disabled by default during power-on reset and is enabled later by software. The
USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock
reference for the USB PLL. The USB PLL is enabled by clearing the USBPWRDN bit of the RCC2
register. The XTAL bit field (Crystal Value) of the RCC register describes the available crystal choices.
The main oscillator must be connected to one of the following crystal values in order to correctly
generate the USB clock: 4, 5, 6, 8, 10, 12, or 16 MHz. Only these crystals provide the necessary
USB PLL VCO frequency to conform with the USB timing specifications.
PLL Modes
Both PLLs have two modes of operation: Normal and Power-Down
■
■
The modes are programmed using the RCC/RCC2 register fields (see page 81 and page 88).
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T
22-8 on page 616) for the main PLL and T
affected PLL is not usable as a clock reference.
Either PLL is changed by one of the following:
■
■
A counter is defined to measure both the T
clocked by the main oscillator. The range of the main oscillator has been taken into account and
the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). When
the XTAL value is greater than 0x0f, the down counter is set to 0x2400 to maintain the required lock
time on higher frequency crystal inputs. Hardware is provided to keep the PLL from being used as
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
Change in the PLL from Power-Down to Normal mode.
Preliminary
USBREADY
READY
and T
for the USB PLL. During the relock time, the
USBREADY
requirements. The counter is
READY
(see Table
June 02, 2008