AD9520-1 Analog Devices, Inc., AD9520-1 Datasheet - Page 57

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AD9520-1

Manufacturer Part Number
AD9520-1
Description
12 Lvpecl/24 Cmos Output Clock Generator With Integrated 2.5 Ghz Vco
Manufacturer
Analog Devices, Inc.
Datasheet

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Table 46. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
DS
DH
CLK
S
C
HIGH
LOW
DV
SCLK
SDIO
CS
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between the SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 66)
t
t
DS
S
BIT N
t
HIGH
t
DH
Figure 68. Serial Control Port Timing—Write
t
CLK
Rev. 0 | Page 57 of 84
t
LOW
BIT N + 1
t
C
AD9520-1

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