74HC175PW,118 NXP Semiconductors, 74HC175PW,118 Datasheet - Page 2

• Manufacturer Part Number: 74HC175PW,118
• Description: IC QUAD D F-F POS-EDGE 16TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCr
• Type: D-Type Busr

Specifications of 74HC175PW,118

• Output Type: Differential
• Package / Case: 16-TSSOP
• Function: Master Reset
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Frequency - Clock: 89MHz
• Delay Time - Propagation: 16ns
• Trigger Type: Positive Edge
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: HC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 17 ns at 5 V
• High Level Output Current: - 5.2 mA
• Low Level Output Current: 5.2 mA
• Supply Voltage (max): 6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74HC175PW-T; 74HC175PW-T; 935174560118

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT175 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
1998 Jul 08
SYMBOL
t
t
f
C
C
PHL
PLH
max
Four edge-triggered D flip-flops
Output capability: standard
I
I
PD
Quad D-type flip-flop with reset; positive-edge trigger
CC
f
f
C
V
For HCT the condition is V
i
o
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
PARAMETER
propagation delay
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop notes 1 and 2
2
CP to Q
MR to Q
CP to Q
MR to Q
= 25 C; t
V
f
o
CC
) = sum of outputs
2
n
n
n
n
, Q
, Q
f
r
i
= t
n
n
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
CONDITIONS
C
2
L
The 74HC/HCT175 have four edge-triggered, D-type
flip-flops with individual D inputs and both Q and Q
outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
All Q
or data inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true
and complement outputs are required and the clock and
master reset are common to all storage elements.
= 15 pF; V
D
in W):
n
outputs will be forced LOW independently of clock
CC
= 5 V
n
HC
17
15
17
15
83
3.5
32
) of the flip-flop.
TYPICAL
74HC/HCT175
Product specification
HCT
16
19
16
16
54
3.5
34
UNIT
ns
ns
ns
ns
MHz
pF
pF