74LVT273PW,112 NXP Semiconductors, 74LVT273PW,112 Datasheet
74LVT273PW,112
Specifications of 74LVT273PW,112
74LVT273PW
935176350112
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74LVT273PW,112 Summary of contents
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V octal D-type flip-flop Rev. 03 — 10 September 2008 1. General description The 74LVT273 is a high-performance BiCMOS product designed for V 3.3 V. This device has eight edge-triggered D-type flip-flops with individual D inputs and Q ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVT273D +125 C 74LVT273DB +125 C 74LVT273PW +125 C 74LVT273BQ +125 C 4. Functional diagram Fig 1. Logic symbol 74LVT273_3 Product data sheet Description SO20 plastic small outline package; 20 leads; body width 7.5 mm SSOP20 plastic shrink small outline package ...
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... NXP Semiconductors CP MR Fig 3. Logic diagram 74LVT273_3 Product data sheet FF1 FF2 FF3 FF5 FF6 FF7 Rev. 03 — 10 September 2008 74LVT273 3.3 V octal D-type flip-fl FF4 FF8 001aae056 © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVT273 GND 10 001aai737 Fig 4. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin 12, 15, 16 13, 14, 17, 18 GND 74LVT273_3 Product data sheet (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input ...
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... NXP Semiconductors 6. Functional description Table 3. Function selection Inputs [ HIGH voltage level HIGH voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition LOW voltage level LOW voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition Don’t care; ...
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... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter I LOW-level output current OL T ambient temperature amb t/ V input transition rise and fall rate; output enabled 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter V input clamping voltage ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC I additional supply current CC C input capacitance I [1] All typical values are measured at V [2] For valid test results data must not be loaded into the flip-flops (or latches) after applying the power. ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter t pulse width W t recovery time rec f maximum frequency max [1] Typical values are measured the same as t and t su su(L) su(H) [ the same as t and t ...
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... NXP Semiconductors MR input CP input Qn output see Table 8 for measurement points. V and V are typical output voltage levels that occur with the output load Fig 7. MR pulse width recovery time and delay CP input Dn input Qn output see Table 8 for measurement points. V and V are typical output voltage levels that occur with the output load. ...
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... NXP Semiconductors Test data is given in given in Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 9. Load circuitry for switching times Table 9. Test data Input V Repetition rate I 2 MHz ...
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... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 11. Package outline SOT339-1 (SSOP20) ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Title changed to 3.3 V octal D-type flip-flop • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history ...