74LVT374PW,112 NXP Semiconductors, 74LVT374PW,112 Datasheet - Page 2

• Manufacturer Part Number: 74LVT374PW,112
• Description: IC OCT D FF POS-EDG TRIG 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr
• Type: D-Type Busr

Specifications of 74LVT374PW,112

• Function: Standard
• Output Type: Non-Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 200MHz
• Delay Time - Propagation: 3.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVT374PW; 74LVT374PW; 935213340112

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
Philips Semiconductors
20-Pin Plastic SOL
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
1998 Feb 19
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
3-State outputs for bus interfacing
Common output enable
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
SYMBOL
C
I
t
t
C
PLH
PHL
CCZ
OUT
IN
PACKAGES
GND
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
Q0
Q1
OE
D0
D1
Q2
D2
D3
Q3
10
1
2
3
4
5
6
7
8
9
PARAMETER
TEMPERATURE RANGE
SA00110
20
19
18
17
16
15
14
13
12
11
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
CC
C
V
V
Outputs disabled;
V
Outputs disabled;
V
L
CC
I
I/O
CC
OUTSIDE NORTH AMERICA
= 0V or 3.0V
= 50pF;
= 0V or 3.0V
= 3.3V
= 3.6V
2
T
DESCRIPTION
The 74LVT374 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74LVT374 is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
PIN DESCRIPTION
74LVT374 PW
74LVT374 DB
amb
74LVT374 D
13, 14, 17,
12, 15, 16,
NUMBER
3, 4, 7, 8,
2, 5, 6, 9,
CONDITIONS
= 25 C; GND = 0V
PIN
18
19
11
10
20
1
SYMBOL
D0-D7
Q0-Q7
GND
V
OE
CP
CC
NORTH AMERICA
74LVT374PW DH
Output enable input (active-Low)
Data inputs
Data outputs
Clock pulse input (active rising edge)
Ground (0V)
Positive supply voltage
74LVT374 DB
74LVT374 D
TYPICAL
FUNCTION
0.13
3.2
3.5
4
7
Product specification
74LVT374
DWG NUMBER
853-1826 18985
SOT163-1
SOT339-1
SOT360-1
UNIT
mA
pF
pF
ns