st2064b Sitronix Technology Corporation, st2064b Datasheet
st2064b
Related parts for st2064b
st2064b Summary of contents
Page 1
... The ST2064B is a RISC CPU based 8-bit microcontroller designed with CMOS silicon gate technology. This single chip microcontroller is useful for translator, databank and other consumer applications. It integrates with SRAM, mask ROM, Ver. 3.0 8 BIT Microcontroller with 64K bytes ROM ...
Page 2
... Ver. 3.0 2/57 ST2064B 5/8/09 ...
Page 3
... XIO 1748.88 GND 1635.49 VDD 1514.63 PA0 1402.79 PA1 1292.17 PA2 1181.54 PA3 1071.65 PA4 959.78 PA5 851.76 PA6 740.07 ST2064B Unit: μ 1175.35 1286.33 1396.57 1507.35 1616.52 1729.50 1838.57 1950.05 2058.16 2166.74 2278.86 2388.89 2499.30 2614.30 2800.08 2800.08 2800.08 2800 ...
Page 4
... RAM VOLTAGE DETECTOR PORT DAC PSG 4/57 NAME X COM8 59.95 COM9 59.95 COM10 59.95 COM11 59.95 COM12 59.95 COM13 59.95 COM14 59.95 COM15 59.95 SEG0 59.95 SEG1 59.95 SEG2 59.95 SEG3 59.95 SEG4 59.95 SEG5 59.95 CPU ROM CLOCK TIMER GENERATOR ST2064B Y 1706.56 1595.40 1486.31 1377.48 1267.67 1156.52 1049.31 937.45 818.02 708.22 595.85 486.77 381.48 269.01 5/8/09 ...
Page 5
... High frequency crystal/resonator oscillator output pin. Connect to external crystal/resonator. P Ground pin P Power supply pin I/O Connect to booster capacitor positive(+) terminal I/O Connect to booster capacitor negative(-) terminal P Multi-level power supply for the liquid crystal drive O Voltage output of booster circuit I Chip test function. Leave it open. P PSG Power 5/57 Description ST2064B 5/8/09 ...
Page 6
... Bit 4 Bit 6/57 Bit 2 Bit Bit Decimal mode flag 1 = Decimal mode 0 = Binary mode Bit Interrupt disable flag 1 = Interrupt disable 0 = Interrupt enable Bit Zero flag 1 = Zero 0 = Non zero Bit Carry flag 1 = Carry 0 = Non carry ST2064B Bit 0 C 5/8/09 ...
Page 7
... I 8.1 Memory map ST2064B builds in 64K bytes ROM and 2K bytes RAM. The internal ROM can be used as data memory or program memory. PRR is the Program ROM Bank Register and DRR is the Data ROM Bank Register. The logical program ROM address is from $4000 to $7FFF(16K bytes), and $8000 to $FFFF (32K bytes) is for logical data ROM address. ...
Page 8
... LSEL[2] LSEL[1] LSEL[0] CTR[2] CTR[1] CTR[0] LCK[2] LCK[1] LCK[0] IRT0 IRDAC IRX IET0 IEDAC IEX ST2064B Default 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 100 - 0000 0000 - - - - 0000 0000 0000 - - - - 0000 0000 0000 -000 0000 ...
Page 9
... After the system has been operating, a low on this line at least of two clock cycles will cease ST2064B activity. When a positive edge is detected, there is an initialization sequence lasting six clock cycles. Then the interrupt mask flag is set, the decimal mode is cleared and the program counter will loaded with the restart vector from locations $7FFC (low byte) and $7FFD (high byte) ...
Page 10
... DAC time out interrupt enable 0 = DAC time out interrupt disable Bit 0: IEX: INTX Interrupt Enable bit 1 = INTX edge interrupt enable 0 = INTX edge interrupt disable 10/57 Bit 2 Bit 1 Bit 0 Default IRT0 IRDAC IRX - - 00 0000 Bit 2 Bit 1 Bit 0 Default IET0 IEDAC IEX - - 00 0000 ST2064B 5/8/09 ...
Page 11
... 10.1 Description ST2064B can supply total 24 GPIOs divided into three I/O ports, Port-A, Port-B, and Port-C. Besides I/O function, Port-B/C can also be used as LCD segment drives. For detail pin assignment, please refer to TABLE 10-1 PORT NAME PAD NAME PA0/INTX PA1 PA2 PA3 ...
Page 12
... Bit 2 Bit 1 Bit 0 PCA[3] PCA[2] PCA[1] PCA[0] appears at input pin. It must be off when reading Port-A. Bit 3 Bit 2 Bit 1 Bit 0 PAK[3] PAK[2] PAK[1] PAK[0] ST2064B Default 1111 1111 0000 0000 0000 0000 100 - 0000 - - 00 0000 Default 0000 0000 Default 0000 0000 5/8/09 ...
Page 13
... Bit 5: INTEG : INTX interrupt edge option bit 1 = Rising edge 0 = Falling edge Bit3: TEST : Test bit, must be “ 0” Ver. 3.0 VCC PULL-UP PMOS RD_INPUT TABLE 10-5 Port Function Control Register (PMCR) Bit 6 Bit 5 Bit 4 Bit 3 PDBN INTEG - TEST 13/57 FIGURE 10-1 Port-A Block Diagram Bit 2 Bit 1 Bit 0 Default - - - 100 - ST2064B 5/8/09 ...
Page 14
... Set input mode. #$FF < PULL-UP. <PA ; Keep last state. <IREQ ; Clear IRQ flag. <IENA ; Enable INT <PA ; Keep last state. DFF D Q XNOR2 OR2 CK DFF Q D XNOR2 CK OR2 DFF D Q XNOR2 CK OR2 DFF D Q XNOR2 CK OR2 PTIR High Level Interrupt NAND8 ST2064B 5/8/09 ...
Page 15
... Port-A Interrupt De-bounce ST2064B has hardware de-bounce block for Port-A interrupt enabled with “ 1” and disable with “ 0” of PDBN(PMCR[6]). The de-bounce function is activated by Port-A transition. It uses TABLE 10-6 Port Function Control Register (PMCR) Address Name R/W Bit 7 $00F PMCR R/W PULL ...
Page 16
... PCC[4] PCC[3] 16/57 Bit 2 Bit 1 Bit 0 Default PB[2] PB[1] PB[0] 1111 1111 PC[2] PC[1] PC[0] 1111 1111 PCB[2] PCB[1] PCB[0] 0000 0000 PCC[2] PCC[1] PCC[0] 0000 0000 - - - 100 - - - - - - - - 1 1111 Bit 2 Bit 1 Bit 0 Default PCB[2] PCB[1] PCB[0] 0000 0000 Bit 2 Bit 1 Bit 0 Default PCC[2] PCC[1] PCC[0] 0000 0000 ST2064B 5/8/09 ...
Page 17
... Disable pull-up function Ver. 3.0 PULL-UP PORT CONTROL REGISTER ( PCR ) PORT DATA REGISTER ( PDR ) DATA INPUT FIGURE 10-4 Port-B and Port-C Block Diagram TABLE 10-10 Port Control Register (PMCR) Bit 6 Bit 5 Bit 4 Bit 3 PDBN INTEG - TEST 17/57 VCC PULL-UP PMOS RD_INPUT Bit 2 Bit 1 Bit 0 Default - - - 100 - - - - - ST2064B 5/8/09 ...
Page 18
... COM8 output =LOW Ver. 3.0 decided by DUTY[1:0] of $39(LSEL), Please refer to the following table. Bit 6 Bit 5 Bit 4 Bit 3 BIAS4 LSEL[4] LSEL[3] LSEL[2] LSEL[1] LSEL[0] TABLE 10-12 COM Output Register (COM) Bit 6 Bit 5 Bit 4 Bit 3 18/57 Bit 2 Bit 1 Bit 0 Default 0001 1111 Bit 2 Bit 1 Bit 0 Default ???? ???? ST2064B 5/8/09 ...
Page 19
... ST2064B has dual clock sources, OSC (RC) and OSCX (32768Hz crystal). The system clock (SYSCK) can be switched between OSC and OSCX, and is controlled by XSEL (SYS[7]). When system clock is switched, the warm-up cycles occur at the same time. Clock source being used is shown at ...
Page 20
... 12.1 Prescaler 12.1.1 Function Description The ST2064B has three timers, Base timer, Timer 0 and Timer 1, and two prescalers PRES and PREW. There are two clock sources, SYSCK and INTX, for PRES and one clock source, Address Name R/W Bit 7 $021 BTM ...
Page 21
... PRES and Timer1 will get a 16bit-event counter. TABLE 12-2 Prescaler Control Register (PRS) Bit 6 Bit 5 Bit 4 Bit 3 PRS[6] PRS[5] PRS[4] PRS[3] SENA SENT - - timer1. It stops counting only if OSCX stops or hardware reset occurs. 21/57 Bit 2 Bit 1 Bit 0 Default PRS[2] PRS[1] PRS[0] 0000 0000 - - - 000 - - - - - ST2064B 5/8/09 ...
Page 22
... Bit - UP Counter IRBT CLOCK OUT Base Timer source clock STOP TCLK / 65536 TCLK / 32768 TCLK / 8192 TCLK / 2048 TCLK / 256 TCLK / 32 TCLK / 8 TCLK / 2 OSCX / 256 OSCX / 64 OSCX / 16 OSCX / 4 ST2064B 5/8/09 ...
Page 23
... Bit 3 Bit 2 Bit 1 Bit 0 T0C[3] T0C[2] T0C[1] T0C[0] ST2064B IRT0 Default 0000 0000 5/8/09 ...
Page 24
... TCLK stop 1 : TCLK counting 24/57 D Flip-Flop OUT D Q SYSCK CK 8 Bit - UP Counter CLOCK Auto Reload Bit 2 Bit 1 Bit 0 T1C[2] T1C[1] T1C[0] T1 Timer Clock Source TCLK/65536 TCLK/32768 TCLK/8192 TCLK/2048 TCLK/256 TCLK/32 TCLK/8 TCLK/2 OSCX/256 OSCX/128 OSCX/64 OSCX/32 ST2064B IRT1 Default 0000 0000 5/8/09 ...
Page 25
... PS: In order to make sure the PSG function is working normally on the EV or Real Chip Board, Please connect PSG‘ s power PVCC to VCC Ver. 3.0 FIGURE 13-1. ST2064B has three playing modes. First is that both channel0 (CH0) and channel1 (CH1) output square type tones. Second is CH0 outputs square tone, and CH1 outputs noise ...
Page 26
... Hz) 26/57 Bit 2 Bit 1 Bit 0 Default 0000 0000 - - - - 0000 0000 0000 - - - - 0000 - - - - 1111 C1EN C0EN DACE=0 - 000 0000 DMD[0] INH DACE=1 - 000 0000 VOL0[2] VOL0[1] VOL0[0] 0000 0000 Bit 2 Bit 1 Bit 0 Default - - - - 1111 Bit 2 Bit 1 Bit 0 Default 0000 0000 ST2064B 5/8/09 ...
Page 27
... C1EN PSGCK Frequency of Channel 1 Tone = PSGCK/(1000H-PCH1[11~0])/2 Ver. 3.0 FIGURE 13-3 and. FIGURE 13-4. 12 Bit Auto-reload Up Counter C0[11~8] OUTPUT C0[7~0] Channel 0 Latch Enable CLOCK FIGURE 13-3 Tone Generator Channel 0 12 Bit Auto-reload Up Counter C1[11~8] OUTPUT C1[7~0] Channel 1 Latch Enable CLOCK FIGURE 13-4 Tone Generator Channel 1 27/57 ST2064B Tone out Tone out 5/8/09 ...
Page 28
... SYSCK x 2 Ver. 3.0 function. Noise or tone function is selected by PRBS. TABLE 13-4 PSG Control Register (PSGC) Bit 6 Bit 5 Bit 4 Bit 3 PCK[2] PCK[1] PCK[0] PRBS PCK[2] PCK[1] PCK[0] DMD[1] DMD[0] 28/57 Bit 2 Bit 1 Bit 0 Default C1EN C0EN DACE=0 - 000 0000 INH DACE=1 - 000 0000 ST2064B 5/8/09 ...
Page 29
... CLOCK FIGURE 13-5 Noise Generator will enable noise generator when PSG is in noise mode PSGOB and PSGO. Positive part of the AC signal is output from PSGO while the negative part is from PSGOB. ST2064B PSGOB PSGO FIGURE 13-6 PSG application circuit 29/57 OUTPUT Noise out Buzzer ST2064B 5/8/09 ...
Page 30
... DAC[1] DAC[ C1EN C0EN DACE DMD[0] INH DACE Bit 2 Bit 1 Bit 0 Default DAC[2] DAC[1] DAC[0] 0000 0000 Bit 2 Bit 1 Bit 0 Default C1EN C0EN DACE=0 - 000 00-0 DMD[0] INH DACE=1 - 000 0000 ST2064B 5/8/09 ...
Page 31
... FIGURE 14-1 DAC Diagram PSG Selector PSGCK Output Select FIGURE 14-2 DAC Clock Source Control PSGC b6, b5, b4 100 100 31/57 BD BDB Reload_DAC PSGC PSGCK SYSCK SYSCK SYSCK SYSCK SYSCK 2MHz) OSC PSG1H, PSG1L 00001111, 00111111 00001111, 10111111 ST2064B 5/8/09 ...
Page 32
... As the value goes from 0 to -64, the duty cycle decreases from 50% high to 0%. PSGOB is inverse of PSGO’ s waveform. Figure 13-3 shows the PSGO waveforms DAC = 32 FIGURE 14-3 Single-Pin Mode Wave Form ST2064B 330 ohm PSGO 32/57 32 64+X 96 64-X DAC = -32 DAC = X SPK 8050 ST2064B 5/8/09 ...
Page 33
... For a positive output value x=0 to 127, PSGO goes high for X segments while PSGOB stays high. For a negative output value x=0 to -127, PSGOB goes low for |X| segments while PSGO stays low DAC = 32 DAC = DAC = -48 DAC = 0 33/57 ST2064B 127 1 DAC = 127 DAC = -128 5/8/09 ...
Page 34
... PSGO goes high for X segments while PSGOB stays low. For a negative output value x=0 to -127, PSGOB goes high for |X| segments while PSGO stays low DAC = 32 DAC = DAC = -48 DAC = 0 ST2064B PSGOB PSGO 34/57 127 32 1 DAC = 127 DAC = -128 Buzzer ST2064B 5/8/09 ...
Page 35
... ST2064B is capable of driving one 1/16 duty, 1/5 bias LCD panel of segment number from (up to 768 dots). LCD block includes display frame buffer ($1000~ $10AF) for storing display data, 16 common and 32 segment dedicated drives. The rest 16 segment drives are shared with two I/O ports, Port-B/C. Data in frame buffer is undefined after power on, so correct frame data should be filled in before turn on display ...
Page 36
... PB7 PB2 PB3 PB4 PB5 PB6 PB7 PB2 PB3 PB4 PB5 PB6 PB7 PB2 PB3 PB4 PB5 PB6 PB7 PB2 PB3 PB4 PB5 PB6 PB7 PB3 PB4 PB5 PB6 PB7 PB4 PB5 PB6 PB7 PB5 PB6 PB7 PB6 PB7 PB7 ST2064B 5/8/09 ...
Page 37
... Bit 2 Bit 1 Bit 0 Default CTR[2] CTR[1] CTR[0] 1000 0000 8 8 (maximum (minimum (maximum (minimum) ST2064B 5/8/09 ...
Page 38
... Frame Rate = 85Hz 0XXX = driving level 8 1000 = driving level 8 (maximum) 1001 = driving level 7 1101 = driving level 3 1110 = driving level 2 (minimum) 1111 = driving level 1 38/57 Bit 2 Bit 1 Bit 0 Default LCK[2] LCK[1] LCK[0] 1111 0000 1/8 Duty consumption (uA) 42.75 40.75 37.75 35.75 33.75 31.75 29.75 26.75 24.75 22.75 20.75 17.75 15.75 13.75 11.75 9.75 (maximum (minimum) (maximum (minimum) ST2064B 5/8/09 ...
Page 39
... Bit 2~0: LCK[2:0] : LCD frame rate control LCK[2:0] 000 001 010 011 100 101 110 111 Ver. 3.0 Clock Source Frame Rate OSCX (32768Hz OSCX (32768Hz OSC (2MHz OSC (2MHz OSC (4MHz OSC (4MHz OSC (8MHz OSC (8MHz 39/57 ST2064B 5/8/09 ...
Page 40
... If there is crosstalk on the first line, please turn on keyboard-scan function for better quality & 40/57 ST2064B 5/8/09 ...
Page 41
... RTI Ver. 3 Sca n Valu t Stab t-A set to r etu r n lin e No 41/57 ST2064B Scan t-B & Set to Nor I/O R ead t-B & Stor Data ...
Page 42
... Bit5 Bit5 … … Bit4 Bit4 Bit3 Bit3 Bit2 Bit2 … … Bit1 Bit1 Bit0 Bit0 1085H 10AFH Bit7 Bit7 … … Bit6 Bit6 Bit5 Bit5 … … Bit4 Bit4 Bit3 Bit3 Bit2 Bit2 … … Bit1 Bit1 Bit0 Bit0 ST2064B 5/8/09 ...
Page 43
... ST2064B has three power down modes: WAI-0, WAI-1 and STP. The instruction WAI will enable either WAI-0 or WAI-1, which is controlled by WAIT(SYS[2]). And the instruction Address Name R/W Bit 7 $030 SYS R/W XSEL Bit 3: WSKP : System warm-up control bit ...
Page 44
... Stop Ver. 3.0 Base OSCX RAM REG. Timer Retain Stop Retain Stop Retain Base OSCX RAM REG. Timer Retain Retain Retain 44/57 LCD I/O Wake-up condition Reset, Any interrupt Reset, Any interrupt Reset LCD I/O Wake-up condition Reset, Any interrupt Reset, Any interrupt Reset ST2064B 5/8/09 ...
Page 45
... ST2064B has a built-in low voltage detector for power management. When LVDET is set, detector circuit is enabled and the detection result will be outputted at the same bit after 3 ms. Using read instruction twice can get this result: first read will enable initial stableness control. ...
Page 46
... No detector voltage adjustment 46/57 Condition All I/O ports are input and pull-up, LCD driving strength is maximum. All I/O ports are input and pull-up, OSCX on, LCD off (WAIT1/STOP mode) All I/O ports are input and pull-up, OSCX on, LCD off (WAIT0 mode) PORT A, PORT B, PORT C PORT A, PORT B, PORT C ST2064B 5/8/09 ...
Page 47
... FIGURE 18-1 Relation between operation voltage & frequency 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 2.2 2.4 2.6 Voltage Freq. 4MHz 2MHz 1MHz 500KHz Ver. 3.0 Voltage & Frequency 2.8 3 3.2 Voltage TABLE 18-1 R-Oscillator V.S. Frequency 3V 110Kohm 260Kohm 570Kohm 1240Kohm 47/57 R=110k R=260K 3.4 3.6 3.8 5V 123Kohm 274Kohm 590Kohm 1220Kohm ST2064B 5/8/09 ...
Page 48
... APPLICATION CIRCUIT WITHOUT LCD KEYBOARD AWAKING PULSE Ver. 3 LCD PANEL SEG[ SEG[47] COM[ COM[15] SEG[ COM[ SEG[47] COM[15] ST2064B CAP1+ CAP1 0.1uF 0.1uF 0.1uF VDD 0.1uF 48/57 ST2064B VDD VDD 0.1uF 4.7uF OSCI 100pF 15pF OSCXO 32768Hz OSCXI 15pF GND 5/8/09 ...
Page 49
... Note: 1. COMs and SEGs output GND level, while the LCD is turned off LCD is turned off, Keyboard Awaking Pulses must be turned off at the same time COM[15] VDD - - - COM[15] VDD 0.1uF OSCI 100pF 15pF OSCXO 32768Hz OSCXI 15pF GND ST2064B 4.7uF 5/8/09 ...
Page 50
... LCD PANEL SEG[ SEG[31] COM[ COM[15] RESET SEG[ SEG[31] COM[ PC0~PC7 PB0~PB7 ST2064B PA0~PA7 PSG1 CAP1+ CAP1- PSG0 VP V2 0.1uF 0.1uF VDD APPLICATION CIRCUIT WITHOUT DC-DC CONVERTER 50/57 VDD VDD COM[15] 0.1uF OSCI 100pF 15pF OSCXO 32768Hz OSCXI 15pF GND V3 ST2064B 4.7uF 5/8/09 ...
Page 51
... ST2064B EVB PCB113-1 FIGURE 19-4 The PCB 113-1 of ST2064B EVB Ver. 3.0 51/57 ST2064B 5/8/09 ...
Page 52
... Low Voltage Detector： Enable PSGO Option PSGOB Option COM[8~15] Option Port-A use as Keyboard(PAK) ST2064B EVB Program file： ﹒ bin E.V. Board bios version： Check sum（ See appendix） ： Appendix： Convert mask code into binary from 0000h ~ FFFFh； ...
Page 53
... Use LCD-EV chip to check LCD display quality. If there is crosstalk 26 on the first line, please turn on keyboard-scan function for better quality. Always disable interrupt function(by an “ SEI ” instruction) when 27 modify the IENAL,IENAH,IREQL and IREQH register 28 After Power on ,enter wait 0 mode 0.5s before normal operation Ver. 3.0 Check 53/57 ST2064B / / Note 5/8/09 ...
Page 54
... ST20P64 has Low Voltage Reset (LVR) function. While the operation voltage is lower than 1.7V, the reset pin will be short to GND to act reset automatically. There is no LVR function in ST2064B. 2 ST20P64 Operation current is double of ST2064B’ PA0 input range (VIH &VIL) is different from ST20P64’ s. (ST20P64: 1.25V,0.89V) (ST2064B: 1.66V,1.44V ST20P64, PA0 pull-up resister is smaller than PA1~7, when the system is operating under 5V ...
Page 55
... Hz.） Contrast Level 1(light 8(dark) IC Power On Default. Ver. 3.0 Equivalent Duty CTR[3:0] 1111 48.8 1110 41.0 1101 35.3 1100 31.0 1011 27.7 1010 25.0 1001 22.8 1000 20.9 0111 19.3 0110 18.0 0101 16.8 0100 16.0 Equivalent Duty CTR[3:0] 1111 36.6 1110 30.7 1101 26.5 1100 23.3 1011 20.8 1010 18.7 1001 17.1 1000 16.0 55/57 ST2064B Bias 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Bias 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5/8/09 ...
Page 56
... PRS[7~0] : The low byte value of PRES counter Page51 Add ST2064B EVB photo Page52 Add checklist for customer to confirm ST2064B EVB PCB number… … … … … … … … … … .… .2007/5/21 Version2.5 P12,13,16,17 Change register PMCR bit3 PARP to Test bit and must be set “ 0” … … … … … … … … 2006/9/19 Version2.4 Page8,19,20,43,45 Change register SYS bit4 XBAK to Test bit and must be set “ ...
Page 57
... First release… … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … 2002/12/11 ST2064B is modified from ST2064 The above information is the exclusive intellectual property of Sitronix Technology Corp ...