CR14 STMicroelectronics, CR14 Datasheet - Page 14

• Manufacturer Part Number: CR14
• Description: Low Cost Iso14443 Type-b Contactless Coupler Chip With Anti-collision And Crc Management
• Manufacturer: STMicroelectronics

3 CR14 registers
3.3
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The Input/Output Frame Register is set to all 00h between transmission and reception. If there
is no answer from the PICC, Byte 0 is set to 00h. In the case of a CRC error, Byte 0 is set to
FFh, and the data Bytes are discarded and not appended in the register.
The CR14 Input/Output Frame Register is so designed as to generate all the ST short range
memory command frames. It can also generate all standardized ISO14443 type-B command
frames like REQB, SLOT-MARKER, ATTRIB, HALT, and get all the answers like ATQB, or
answer to ATTRIB. All ISO14443 type-B compliant PICCs can be accessed by the CR14
provided that their data frame exchange is not longer than 35 Bytes in both request and answer.
Table 4.
Slot Marker Register (03h)
The slot Marker Register is located at the I²C address 03h. It is used to trigger an automated
anti-collision sequence between the CR14 and any ST short range memory present in the
electromagnetic field. With one I²C access, the CR14 launches a complete stream of
commands starting from PCALL16(), SLOT_MARKER(1), SLOT_MARKER(2) up to
SLOT_MARKER(15), and stores all the identified Chip_IDs into the Input/Output Frame
Register (I²C address 01h).
This automated anti-collision sequence simplifies the host software development and reduces
the time needed to interrogate the 16 slots of the STMicroelectronics anti-collision mechanism.
When accessed in I²C Write mode, the Slot Marker Register starts generating the sequence of
anti-collision commands. After each command, the CR14 wait for the ST short range memory
answer frame which contains the Chip_ID. The validity of the answer is checked and stored into
the corresponding Status Slot Bit (Byte 1 and Byte 2 as described in
correct, the Status Slot Bit is set to ‘1’ and the Chip_ID is stored into the corresponding
Slot_Register. If no answer is detected, the Status Slot Bit is set to ‘0’, and the corresponding
Slot_Register is set to 00h. If a CRC error is detected, the Status Slot Bit is set to ‘0’, and the
corresponding Slot_Register is set to FFh.
Each time the Slot Marker Register is accessed in I²C Write mode, Byte 0 of the Input/Output
Frame Register is set to 18, Bytes 1 and 2 provide Status Bits Slot information, and Bytes 3 to
18 store the corresponding Chip_ID or error code.
The Slot Marker Register cannot be accessed in I²C Read mode. All the anti-collision data can
be accessed by reading the Input/Output Frame Register at the I²C address 01h.
Frame Length
00h No Byte transmitted
FFh CRC Error
xxh Number of transmitted Bytes
Byte 0
Input/Output Frame Register Description
First data Byte
<------------- Request and Answer Frame Bytes exchanged on the RF ------------->
Byte 1
Second data Byte
Byte 2
Byte 3
...
Table
Byte 34
6). If the answer is
Last data Byte
Byte 35
CR14