cs8413-cs Cirrus Logic, Inc., cs8413-cs Datasheet
cs8413-cs
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cs8413-cs Summary of contents
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... The CS8414 de-multiplexes the channel, user, and va- lidity data directly to serial output pins with dedicated output pins for the most important channel status bits. ORDERING INFORMATION CS8413-CS CS8414-CS VA+ FILT AGND MCK ...
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... TABLE OF CONTENTS CHARACTERISTICS/SPECIFICATIONS ............................................................ 3 RECOMMENDED OPERATING CONDITIONS .......................................... 3 DIGITAL CHARACTERISTICS.................................................................... 3 DIGITAL CHARACTERISTICS - RS422 RECEIVERS................................ 4 SWITCHING CHARACTERISTICS - CS8413 PARALLEL PORT............... 4 SWITCHING CHARACTERISTICS - SERIAL PORTS................................ 5 GENERAL DESCRIPTION .................................................................................. 7 Line Receiver .............................................................................................. 7 Clocks and Jitter Attenuation ...................................................................... 7 CS8413 DESCRIPTION ....................................................................................... 8 Parallel Port ................................................................................................ 8 Status and IEnable Registers ..................................................................... 9 Control Registers ...................................................................................... 11 Audio Serial Port ....................................................................................... 14 Normal Modes ...
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... VD+, VA ± 5%) A Symbol except RXP, RXN V IH except RXP, RXN 200 µA) V (VD -3.2 mA (Note (Note 3) MCK t j CS8413 CS8414 Min Max Units - 6 ±10 mA -0.3 (VD+) + 0 -55 125 °C -65 150 °C Min Typ Max Units 4.75 5.0 5.25 ...
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... RXP to RXN to exceed 200 mV. This represents twice the minimum signal level of 200 mVp-p specified in CP340/1201 and IEC-958 (which are not RS-422 compliant). SWITCHING CHARACTERISTICS - CS8413 PARALLEL PORT ( °C;VD+, VA ± 5%; Inputs: Logic 0 = DGND, Logic 1 = VD+; C ...
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... The table above assumes data is output on the falling edge and latched on the rising edge. With the CS8413 the edge is selectable. The table is defined for the CS8413 with control reg. 2 bit 0, SCED, set to one, and for the CS8414 in formats and 7. For the other formats, the table and figure edges must be reversed (i.e. “ ...
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... Error/Frequency 27, 2-6 Reporting 470 0.068 µF 6 +5V Analog +5V Digital 22 7 VA+ VD+ 21 AGND FSYNC 9 RXP SDATA 10 RXN CS8413 20 FILT RD/WR D0-D7 DGND 8 Figure 1. CS8413 Typical Connection Diagram +5V Analog +5V Digital 22 7 VA+ VD+ 21 AGND 9 RXP SDATA FSYNC 10 RXN CS8414 13 CS12/FCK 16 SEL 25 ERF 6 C/E-F bits 20 FILT DGND 8 Figure 2. CS8414 Typical Connection Diagram CS8413 CS8414 0.1 µ ...
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... CS8411/12 digital audio receiver parts. The func- tionality of the CS8413/14 is the same as the CS8411/12 with two exceptions: first, the operat- ing frequency (sample rate) of the CS8413/14 is ex- tended to include 96 kHz, and second, the frequency reporting bits are modified to delete the ±400 ppm ranges, and include 88.2 kHz and 96 kHz ranges ...
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... FSYNC from MCK instead of from the incoming data. CS8413 DESCRIPTION The CS8413 is more flexible than the CS8414 but requires a microcontroller or DSP to load internal registers. The CS8414 does not have internal regis- ters so it may be used in a stand-alone mode where a microprocessor or DSP is not available ...
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... De-Multiplexor crc check Frequency Comparator Figure 4. CS8413 Block Diagram used to monitor the ram buffer. These bits continu- ally change and indicate the position of the buffer pointer which points to the buffer memory location currently being written. Each flag has a corre- sponding interrupt enable bit in IEnable register 1 which, when set, allows a transition on the flag to generate a pulse on the interrupt pin ...
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... AND’ed with their associated interrupt enable bits in IEnable register 2. SLIP is only valid when the audio port is in slave mode (FSYNC and SCK are inputs to the CS8413). This flag is set when an audio sample is dropped or 10 X:00 X:00 SR1 ...
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... Bit 5 is unused and bits 6 and 7, the two most significant bits, are factory test bits and must be set to zero when writing to this register. The CS8413 sets these bits to zero on pow- er-up. Control Registers The CS8413 contains two control registers. Control ...
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... When set, falling edge of SCK outputs data. When clear, rising edge of SCK outputs data. Figure 9. Control Register 2 ROER, when set, causes the last audio sample to be reread if the error pin, ERF, is active. When out of lock, the CS8413 will output zeros if ROER is set Reserved ...
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... DS240F1 data can be read twice or missed if the device con- trolling FSYNC and SCK different time- base than the CS8413. If the audio data is read twice or missed, the SLIP bit in SR1 is set. SCED selects the SCK edge to output data on. SCED high causes data to be output on the falling edge, and SCED low causes data to be output on the rising edge ...
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... FSYNC output modes. If the circuit generating SCK and FSYNC is not locked to the master clock of the CS8413, the serial port will eventually be re- read or a sample will be missed. When this occurs, the SLIP bit in SR1 will be set. ...
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... FLAG0 will generate a low pulse on the interrupt pin. The level of FLAG0 indicates DS240F1 CS8413 CS8414 which two bytes the part will write next, thereby in- dicating which two bytes are free to be read. FLAG1 is buffer mode dependent and is discussed in the individual buffer mode sections ...
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... LSB Audio Data Figure 11. CS8413 Status Register Flag Timing channel status data is independent for each channel. A block of CS data is defined as one bit per frame, not one bit per sub-frame; therefore, there are two blocks of channel status. The CS2/CS1 bit in CR1 selects which channel is stored in the buffer ...
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... User Addr Figure 12. CS8413 Buffer Memory Write Sequence - MODE 0 DS240F1 cyclic buffer for the last 20 bytes of channel status data. The channel status buffer is divided in this fashion because the first four bytes are the most im- portant ones; whereas, the last 20 bytes are often not used (except for byte 23, CRC) ...
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... C.S. Byte C.S. Address FLAG1 FLAG0 C.S. Addr User Addr Aux. Addr 13,14 17 Figure 13. CS8413 Buffer Memory Write Sequence - MODE 1 FLAG2 FLAG1 FLAG0 C.S. Byte Left C.S. Ad Right C.S. Ad. FLAG1 FLAG0 Left C.S. Ad. 08 Right C.S. Ad. 10 User Address ...
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... Buffer Updates and Interrupt Timing As mentioned previously in the buffer mode sec- tions, conflicts between externally reading the buffer RAM and the CS8413 internally writing to it may be averted by using the flag levels to avoid the section currently being addressed by the part. How- ever, if the interrupt line, along with the flags, is utilized, the actual byte that was just updated can be determined ...
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... CS8414 is illustrated in Figure 16. The line receiver and jitter performance are de- scribed in the sections directly preceding the CS8413 sections in the beginning of this data sheet. Audio Serial Port The audio serial port is used primarily to output au- dio data and consists of three pins: SCK, FSYNC, and SDATA ...
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... Format 14 is reserved and not presently used, and format 15 causes the CS8414 to go into a reset state. While in reset all outputs will be inactive except MCK. The CS8414 comes out of reset at the first block boundary after CS8413 CS8414 M1 M0 Format 0 ...
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... MSB LSB Left LSB MSB LSB 16 Bits Left LSB LSB MSB 18 Bits Left MSB LSB MSB Figure 17. CS8414 Audio Serial Port Formats CS8413 CS8414 Right MSB LSB MSB Right MSB LSB MSB Right MSB LSB MSB Right MSB LSB Right LSB ...
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... ERF to go high: a parity error or biphase cod- ing violation during that sample out of lock PLL receiver. Timing for the above pins is illustrat Figure 19. Right 0 Left 1 Right 31 Figure 19. CBL Timing CS8413 CS8414 Right AUX LSB MSB Right AUX LSB ...
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... Channel Status Reporting When SEL is high, channel status is displayed on C0, and Ca-Ce for the channel selected by CS12. If CS12 is low, channel status for sub-frame 1 is dis- played, and if CS12 is high, channel status for sub- frame 2 is displayed. The contents of Ca-Ce depend CS8413 CS8414 F1 F0 Sample Frequency 0 0 ...
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... There are two category codes that get spe- No Emphasis cial attention: general and A/D converters without Not Indicated bit information. For these two categories the SCMS standard requires that equipment interfacing to these categories set the C bit to 0 (copyright pro- CS8413 CS8414 25 ...
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... L bit to 1 (original). To support this feature, Ce, in the consumer mode, is defined as IGCAT (ignorant category) which is low for the “general” (0000000) and “A/D converter without copyright information” (01100xx) catego- ries. 26 CS8413 CS8414 DS240F1 ...
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... PIN DESCRIPTIONS: CS8413 DATA BUS BIT 2 DATA BUS BIT 3 DATA BUS BIT 4 DATA BUS BIT 5 DATA BUS BIT 6 DATA BUS BIT 7 DIGITAL POWER DIGITAL GROUND RECEIVE POSITIVE RECEIVE NEGATIVE FRAME SYNC SERIAL DATA CLOCK ADDRESS BUS BIT 4/FCLOCK INTERRUPT Power Supply Connections VD+ - Positive Digital Power, PIN 7 ...
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... Parallel port address bus that selects the internal memory location to be read from or written to. Note that A4 is the dual function pin A4/FCK as described above. D0-D7 - Data Bus, PINS 27-28, 1-6. Parallel port data bus used to check status, read or write control words, or read internal buffer memory. 28 CS8413 CS8414 DS240F1 ...
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... RS422 compatible line receivers. Described in detail in Appendix A. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 470 resistor and 0.068µF capacitor are required from the FILT pin to analog ground. DS240F1 CS8413 CS8414 29 ...
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... SCK CS12/FCK 13 16 SEL CBL CS8413 CS8414 VALIDITY + ERROR FLAG CS e/FREQ REPORT 2 SERIAL OUTPUT DATA ERROR FLAG SERIAL PORT MODE SELECT 1 SERIAL PORT MODE SELECT 0 ANALOG POWER ANALOG GROUND FILTER MASTER CLOCK SERIAL PORT MODE SELECT 2 SERIAL PORT MODE SELECT 3 ...
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... The channel status block output is high for the first four bytes of channel status and low for the last 20 bytes. SEL - Select, PIN 16. Control pin that selects either channel status information (SEL = 1) or error and frequency information (SEL = displayed on six of the following pins. DS240F1 CS8413 CS8414 31 ...
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... RS422 compatible line receivers. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 470 resistor and 0.068µF capacitor is required from FILT pin to analog ground. 32 CS8413 CS8414 DS240F1 ...
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... SEATING PLANE e DIM DS240F1 D INCHES MIN MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.697 0.713 17.70 0.291 0.299 0.040 0.060 0.394 0.419 10.00 0.016 0.050 0° 8° CS8413 CS8414 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 18.10 7.40 7.60 1.02 1.52 10.65 0.40 1.27 0° 8° 33 ...
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... APPENDIX A: RS422 RECEIVER INFORMATION The RS422 receivers on the CS8413 and CS8414 are designed to receive both the professional and consumer interfaces, and meet all specifications listed in the digital audio standards. Figure A20 il- lustrates the internal schematic of the receiver por- tion of both chips. The receiver has a differential input ...
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... Coax Figure 23. Consumer Input Circuit DS240F1 TTL/CMOS Levels The circuit shown in Figure A24 may be used when external RS422 receivers or TTL/CMOS logic drive the CS8413/14 receiver section. Transformers Please refer Application Note AN134: AES and S/PDIF Recommended Transformers for further information. CS8413/14 0.01 µ ...
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... This is accomplished by pulling all four Figure 25. CS8414 Reset Circuit Mode Select pins high. Figure 25 shows a simple circuit to implement this. The OR gates can be 74LS32 type gates. CS8413 CS8414 RESET DS240F1 ...
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Notes • ...
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