cs8413-cs Cirrus Logic, Inc., cs8413-cs Datasheet - Page 31

• Manufacturer Part Number: cs8413-cs
• Description: 96 Khz Digital Audio Receivers
• Manufacturer: Cirrus Logic, Inc.

Audio Output Interface
SCK - Serial Clock, PIN 12.
FSYNC - Frame Sync, PIN 11.
SDATA - Serial Data, PIN 26.
M0, M1, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17.
Control Pins
VERF - Validity + Error Flag, PIN 28.
U - User Bit, PIN 14.
C - Channel Status Output, PIN 1.
CBL - Channel Status Block Start, PIN 15.
SEL - Select, PIN 16.
DS240F1
Serial clock for SDATA pin which can be configured (via the M0, M1, M2, and M3 pins) as
an input or output, and can sample data on the rising or falling edge. As an output, SCK will
generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample must
be provided in all normal modes.
Delineates the serial data and may indicate the particular channel, left or right, and may be an
input or output. The format is based on M0, M1, M2, and M3 pins.
Audio data serial output pin.
Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3 selects
between eight normal modes (M3 = 0), and six special modes (M3 = 1).
A logical OR’ing of the validity bit from the received data and the error flag. May be used by
interpolation filters to interpolate through errors.
Received user bit serial output port. FSYNC may be used to latch this bit externally. (Except in
I
Received channel status bit serial output port. FSYNC may be used to latch this bit externally.
(Except in I
The channel status block output is high for the first four bytes of channel status and low for the
last 20 bytes.
Control pin that selects either channel status information (SEL = 1) or error and frequency
information (SEL = 0) to be displayed on six of the following pins.
2
S modes when this pin is updated on the active edge of FSYNC.)
2
S modes when this pin is updated on the active edge of FSYNC.)
CS8413 CS8414
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