ir3092 International Rectifier Corp., ir3092 Datasheet - Page 14

• Manufacturer Part Number: ir3092
• Description: 2 Phase Opteron, Athlon, Or Vr10.x Control Ic
• Manufacturer: International Rectifier Corp.

IR3092
Power Good Output
The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft
start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.75V. The PWRGD pin
becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in operation and has no
fault, but does not ensure the output voltage is within the specification. Output voltage regulation within the design limits
can logically be assured however, assuming no component failure in the system.
Tri-State Gate Drivers
The gate drivers can deliver over 3.5A peak current. An adaptive non-overlap circuit monitors the voltage on the GATEHX
and GATELX pins to prevent MOSFET shoot-through current while minimizing body diode conduction.
The Error Amplifier output of the Control IC drives low in response to any fault condition such as VCC input under voltage
or output overload. The 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state operation
prevents negative inductor current and negative output voltage during power-down.
The Gate Drivers revert to a high impedance “off” state at VCCL and VCCHX supply voltages below the normal operating
range. An 80k
to leakage or other cause under these conditions.
Over Voltage Protection (OVP)
The output Over-Voltage Protection comparator monitors the output voltage through the FB pin, the positive remote
sense point. If FB exceeds VDAC plus 145mV (for VR10.X, 480mV for OPTERON and ATHLON, selected with the
VID_SEL pin), both GATEL pins drive high and the OVP pin sources up to 10mA. The OVP circuit over-rides the normal
PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will
remain ON until the over-voltage condition ceases. The lower MOSFETs alone can not clamp the output voltage however
an SCR or N-MOSFET could be triggered by the OVP pin to prevent processor damage.
Error Amplifier compensation can slow down the response to an OVP condition if the voltage loop is too slow, which is
usually not the case. The FB pin can only respond to an over-voltage condition once the EAOUT voltage has reached its
minimum. Until then, the FB pin is modified by the falling EAOUT voltage so FB is equal to VDAC. The Error Amplifier
compensation slew current generates a voltage across the RFB resistor that will mask the output voltage OVP condition.
Again, for a typical fast voltage loop compensation scheme, a fairly large resistor is placed in series with the EAOUT to
FB compensation capacitor to speed up the loop which results in no noticeable OVP sensing delay.
The overall system must be considered when designing for OVP. In many cases the over-current protection of the AC-DC
or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without
damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not
possible, a fuse can be added in the input supply to the multiphase converter. One scenario to be careful of is where the
input voltage to the multiphase converter may be pulled below the level where the ICs can provide adequate voltage to
the low side MOSFET thus defeating OVP.
TM
A Body Braking
Disable Comparator has been included to prevent false OVP firing during dynamic VID down changes.
TM
The BB DISABLE Comparator disables Body Braking
when FB exceeds VDAC by 80mV. The low side MOSFETs will
then be controlled to keep V(FB) and V(VOUT) within 80mV of V(VDAC), below the 150mV INTEL OVP trip point.
Page 14 of 37
06/25/04